Chi-Ying Tsui
Orcid: 0000-0002-8024-2637Affiliations:
- Hong Kong University of Science and Technology
According to our database1,
Chi-Ying Tsui
authored at least 224 papers
between 1992 and 2023.
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Bibliography
2023
A Tiny Accelerator for Mixed-Bit Sparse CNN Based on Efficient Fetch Method of SIMO SPad.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
How Robust is Federated Learning to Communication Error? A Comparison Study Between Uplink and Downlink Channels.
CoRR, 2023
A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications.
CoRR, 2023
Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications.
IEEE Access, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the IEEE Globecom Workshops 2023, 2023
BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
NOLS: A Near-sensor On-chip Learning System with Direct Feedback Alignment for Personalized Wearable Heart Health Monitoring.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
A Primary Driver with Real-Time Resonance Tracking for Wireless-Powered Implantable Medical Devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Binary is All You Need: Ultra-Efficient Arrhythmia Detection with a Binary-Only Compressive System.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Design Strategy of Off-Resonant Tertiary Coils for Uplink Detection in Biomedical Implants.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE Global Communications Conference, 2022
TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
A Reconfigurable Winograd CNN Accelerator with Nesting Decomposition Algorithm for Computing Convolution with Large Filters.
CoRR, 2021
2020
IEEE Wirel. Commun. Lett., 2020
A Low-Power Motion Estimation Architecture for HEVC Based on a New Sum of Absolute Difference Computation.
IEEE Trans. Circuits Syst. Video Technol., 2020
A 40.68-MHz Active Rectifier With Hybrid Adaptive On/Off Delay-Compensation Scheme for Biomedical Implantable Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A Fully Dynamic Multi-Mode CMOS Vision Sensor With Mixed-Signal Cooperative Motion Sensing and Object Segmentation for Adaptive Edge Computing.
IEEE J. Solid State Circuits, 2020
A 6.78-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage Charging Technique.
IEEE J. Solid State Circuits, 2020
Tight Compression: Compressing CNN Model Tightly Through Unstructured Pruning and Simulated Annealing Based Permutation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices Applications.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
IEEE Trans. Multim., 2019
IEEE Trans. Ind. Electron., 2019
IEEE Trans. Circuits Syst. Video Technol., 2019
Design of Sub-Gigahertz Reconfigurable RF Energy Harvester From -22 to 4 dBm With 99.8% Peak MPPT Power Efficiency.
IEEE J. Solid State Circuits, 2019
SubMac: Exploiting the subword-based computation in RRAM-based CNN accelerator for energy saving and speedup.
Integr., 2019
A 2.2μW 600kHz Frequency-Locked Relaxation Oscillator with 0.046%/V Voltage and 48.69ppm/°C Temperature Stability for IoT Sensor Node Applications.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 6.78MHz 92.3%-Peak-Efficiency Single-Stage Wireless Charger with CC-CV Charging and On-Chip Bootstrapping Techniques.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimation.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size.
IEEE Trans. Signal Process., 2018
Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes.
IEEE Trans. Signal Process., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 10.6 pJ⋅K<sup>2</sup> Resolution FoM Temperature Sensor Using Astable Multivibrator.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 2PJ/Pixel/Direction MIMO Processing Based CMOS Image Sensor for Omnidirectional Local Binary Pattern Extraction and Edge Detection.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
An Indoor Solar Energy Harvester with Ultra-Low-Power Reconfigurable Power-On-Reset-Styled Voltage Detector.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
A Simplified PWM Controller for Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Chopper Capacitively Coupled Instrumentation Amplifier Capable of Handling Large Electrode Offset for Biopotential Recordings.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Wireless Power Transfer System With ΣΔ-Modulated Transmission Power and Fast Load Response for Implantable Medical Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 6.78-MHz Single-Stage Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier.
IEEE J. Solid State Circuits, 2017
A low-offset dynamic comparator with area-efficient and low-power offset cancellation.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An implementation of list successive cancellation decoder with large list size for polar codes.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
A wireless power receiver with a 3-level reconfigurable resonant regulating rectifier for mobile-charging applications.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling.
ACM Trans. Design Autom. Electr. Syst., 2016
A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE J. Sel. Areas Commun., 2016
BiLink: A high performance NoC router architecture using bi-directional link with double data rate.
Integr., 2016
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
21.7 A 6.78MHz 6W wireless power receiver with a 3-level 1× / ½ × / 0× reconfigurable resonant regulating rectifier.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A WLAN 2.4-GHz RF energy harvesting system with reconfigurable rectifier for wireless sensor network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
An indoor solar energy harvesting system using dual mode SIDO converter with fully digital time-based MPPT.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Low-Complexity List Successive-Cancellation Decoding of Polar Codes Using List Pruning.
Proceedings of the 2016 IEEE Global Communications Conference, 2016
LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Reconfigurable Resonant Regulating Rectifier With Primary Equalization for Extended Coupling- and Loading-Range in Bio-Implant Wireless Power Transfer.
IEEE Trans. Biomed. Circuits Syst., 2015
A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices.
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
12.8 Wireless power transfer system using primary equalizer for coupling- and load-range extension in bio-implant applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
UHF energy harvesting system using reconfigurable rectifier for wireless sensor network.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A fast variable block size motion estimation algorithm with refined search range for a two-layer data reuse scheme.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
2014
A Novel Single-Inductor Dual-Input Dual-Output DC-DC Converter With PWM Control for Solar Energy Harvesting System.
IEEE Trans. Very Large Scale Integr. Syst., 2014
An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation.
IEEE Trans. Signal Process., 2014
A 13.56MHz wireless power transfer system with reconfigurable resonant regulating rectifier and wireless power control for implantable medical devices.
Proceedings of the Symposium on VLSI Circuits, 2014
An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Proceedings of the IEEE 16th International Workshop on Multimedia Signal Processing, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Found. Trends Electron. Des. Autom., 2013
A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, 2013
Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial).
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Low-Complexity Rotated QAM Demapper for the Iterative Receiver Targeting DVB-T2 Standard.
Proceedings of the 76th IEEE Vehicular Technology Conference, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IET Comput. Digit. Tech., 2011
A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power Energy Harvesting Applications.
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011
Design and analysis of on-chip charge pumps for micro-power energy harvesting applications.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
A low-complexity image compression algorithm for Address-Event Representation (AER) PWM image sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 18th IEEE International Conference on Image Processing, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Joint Routing and Sleep Scheduling for Lifetime Maximization of Wireless Sensor Networks.
IEEE Trans. Wirel. Commun., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE J. Solid State Circuits, 2010
A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band control.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
System level power optimizations for EPC RFID tags to improve sensitivity using load power shaping and operation scheduling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Maximizing the harvested energy for micro-power applications through efficient MPPT and PMU design.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation.
IEEE J. Solid State Circuits, 2009
A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications.
IEEE J. Solid State Circuits, 2008
Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping.
Integr., 2008
A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
An energy-adaptive MPPT power management unit for micro-power vibration energy harvesting.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Integrated single-inductor dual-input dual-output boost converter for energy harvesting applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
2007
Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Corrections to "Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications" [Jan 07 153-166].
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A micro power management system and maximum output power control for solar energy harvesting applications.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
An Inductor-less Micro Solar Power Management System Design for Energy Harvesting Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Proceedings of the 64th IEEE Vehicular Technology Conference, 2006
A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A charge based computation system and control strategy for energy harvesting applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Energy-aware optimal workload allocation among the battery-powered devices to maximize the co-operation life time.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems.
Proceedings of the 43rd Design Automation Conference, 2006
Ultra-low voltage power management circuit and computation methodology for energy harvesting applications.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
A programmable integrated digital controller for switching converters with dual-band switching and complex pole-zero compensation.
IEEE J. Solid State Circuits, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A Data Discarding Framework for Reducing the Energy Consumption of Viterbi Decoder in Decoding Broadcasted Wireless Multi-Resolution JPEG2000 Images.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005
Proceedings of the 2005 Design, 2005
2004
An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction.
IEEE J. Solid State Circuits, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Least leakage vector assisted technology mapping for total power optimization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Adaptive spectrum-based variable bit truncation of discrete cosine transform (DCT) for energy-efficient wireless multimedia communication.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004
Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus.
Proceedings of the 2004 Design, 2004
Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode.
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Single-inductor dual-input dual-output switching converter for integrated battery charging and power regulation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Design and implementation of high-speed arbiter for large scale VOQ crossbar switches.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Proceedings of the 55th IEEE Vehicular Technology Conference, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21, 2002
2001
Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling.
Proceedings of ASP-DAC 2001, 2001
2000
Wirel. Pers. Commun., 2000
IEEE Trans. Circuits Syst. Video Technol., 2000
Proceedings of the 2000 IEEE Wireless Communications and Networking Conference, 2000
Low complexity VLSI implementation of a joint successive interference cancellation with interleaving scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
A low power VLSI architecture of SOVA-based turbo-code decoder using scarce state transition scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
A reduced complexity implementation of the Log-Map algorithm for turbo-codes decoding.
Proceedings of the IEEE International Conference on Acoustics, 2000
Proceedings of the Global Telecommunications Conference, 2000. GLOBECOM 2000, San Francisco, CA, USA, 27 November, 2000
Proceedings of ASP-DAC 2000, 2000
Proceedings of ASP-DAC 2000, 2000
1999
Adaptive tracking of optimal bit and power allocation for OFDM systems in time-varying channels.
Proceedings of the 1999 IEEE Wireless Communications and Networking Conference, 1999
Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Integr., 1998
Int. J. Imaging Syst. Technol., 1998
Towards the capability of providing power-area-delay trade-off at the register transfer level.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
An efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the 34st Conference on Design Automation, 1997
1996
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
IEEE Trans. Very Large Scale Integr. Syst., 1996
Proceedings of the 33st Conference on Design Automation, 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
1994
Power efficient technology decomposition and mapping under an extended power consumption model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
IEEE Des. Test Comput., 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs.
Proceedings of the 31st Conference on Design Automation, 1994
Lower Power Architecture Design and Compilation Techniques for High-Performance Processors.
Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994
1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
Proceedings of the 29th Design Automation Conference, 1992