Yuequan Liu

According to our database, Yuequan Liu authored at least 5 papers between 2015 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2017

Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process.

Yuan Wang, Yuequan Liu, Song Jia, Xing Zhang

Int. J. Circuit Theory Appl., 2017

2016

Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics.

Yuan Wang, Yuequan Liu, Mengyin Jiang, Song Jia, Xing Zhang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance.

Yuequan Liu, Yuan Wang, Song Jia, Xing Zhang

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A reference-less all-digital burst-mode CDR with embedded TDC.

Mengyin Jiang, Yuan Wang, Baoguang Liu, Yuequan Liu, Song Jia, Xing Zhang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation.

Fangyuan Dang, Yuan Wang, Yuequan Liu, Song Jia, Xing Zhang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015