Yuji Osaki

According to our database, Yuji Osaki authored at least 13 papers between 2010 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit.

Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Electron., 2014

2013

1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs.

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

IEEE J. Solid State Circuits, 2013

A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation.

Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto, Takao Onoye

IEICE Electron. Express, 2013

2012

A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs.

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

IEEE J. Solid State Circuits, 2012

A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator.

Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A low-power single-slope analog-to-digital converter with digital PVT calibration.

Yuji Osaki, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs.

Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique.

Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Electron., 2011

Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit.

Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Electron., 2011

A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs.

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

IEICE Electron. Express, 2011

A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs.

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder.

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities.

Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 36th European Solid-State Circuits Conference, 2010