Tetsuya Hirose

According to our database, Tetsuya Hirose authored at least 101 papers between 1993 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Noise-Masking Cryptosystem Using Watermark and Chain Generation for EEG Measurement with Compressed Sensing.

Ryota Tsunaga, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

Utilizing Previously Acquired BSBL Algorithm Parameters in the Compressed Sensing Framework for EEG Measurements.

Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2023

A Triturated Sensing System.

Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Random Undersampling Wireless EEG Measurement Device using a Small TEG.

Takuya Miyata, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

EEG Measurements with Compressed Sensing Utilizing EEG Signals as the Basis Matrix.

Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Programmable Differential Bandgap Reference for Ultra-Low-Power IoT Edge Node Devices.

Yoshinori Itotagawa, Koma Atsumi, Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Sub-30-mV-Supply, Fully Integrated Ring Oscillator Consisting of Recursive Stacking Body-Bias Inverters for Extremely Low-Voltage Energy Harvesting.

Hikaru Sebe, Tomohisa Okumura, Shintaro Sumi, Daisuke Kanemoto, Po-Hung Chen, Tetsuya Hirose

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

Compressed Sensing EEG Measurement Technique with Normally Distributed Sampling Series.

Yuki Okabe, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., October, 2022

Image Quality Improvement for Capsule Endoscopy Based on Compressed Sensing with K-SVD Dictionary Learning.

Yuuki Harada, Daisuke Kanemoto, Takahiro Inoue, Osamu Maida, Tetsuya Hirose

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

Sub-50-mV Charge Pump and its Driver for Extremely Low-Voltage Thermal Energy Harvesting.

Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Multi-Category Image Super-Resolution with Convolutional Neural Network and Multi-Task Learning.

Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa

IEICE Trans. Inf. Syst., 2021

A 35-mV supply ring oscillator consisting of stacked body bias inverters for extremely low-voltage LSIs.

Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose

IEICE Electron. Express, 2021

2020

A 115× Conversion-Ratio Thermoelectric Energy-Harvesting Battery Charger for the Internet of Things.

Ming-Jie Chung, Tetsuya Hirose, Takahito Ono, Po-Hung Chen

IEEE Trans. Circuits Syst., 2020

Design of Switched-Capacitor Voltage Boost Converter for Low-Voltage and Low-Power Energy Harvesting Systems.

Tetsuya Hirose, Yuichiro Nakazawa

IEICE Trans. Electron., 2020

Improvement of Luminance Isotropy for Convolutional Neural Networks-Based Image Super-Resolution.

Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

An 11.8 nA ultra-low power active diode using a hysteresis common gate comparator for low-power energy harvesting systems.

Kaori Matsumoto, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose

IEICE Electron. Express, 2020

Detecting tampered regions in JPEG images via CNN.

Kunihiko Taya, Nobutaka Kuroki, Naoto Takeda, Tetsuya Hirose, Masahiro Numa

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting.

Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2019

Sub-0.1V Input, Low-Voltage CMOS Driver Circuit for Multi-Stage Switched Capacitor Voltage Boost Converter.

Masaya Nishi, Yuichiro Nakazawa, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment.

Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

A Sub-1-µs Start-Up Time, Fully-Integrated 32-MHz Relaxation Oscillator for Low-Power Intermittent Systems.

Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Electron., 2018

An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems.

Kaori Matsumoto, Tetsuya Hirose, Hiroki Asano, Yuto Tsuji, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes.

Ryo Shirai, Tetsuya Hirose, Masanori Hashimoto

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting.

Yuichiro Nakazawa, Tetsuya Hirose, Toshihiro Ozaki, Yuto Tsuji, Shuto Kanzaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Switched-Capacitor Voltage Buck Converter with Step-Down-Ratio and Clock-Frequency Controllers for Ultra-Low-Power IoT Devices.

Shuto Kanzaki, Tetsuya Hirose, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs.

Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Kyohei Shinonaga, Nobutaka Kuroki, Masahiro Numa

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Multi-Channel Convolutional Neural Networks for Image Super-Resolution.

Shinya Ohtani, Yu Kato, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Near-field dual-use antenna for magnetic-field based communication and electrical-field based distance sensing in mm3-class sensor node.

Ryo Shirai, Jin Kono, Tetsuya Hirose, Masanori Hashimoto

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An area-efficient, 0.022-mm2, fully integrated resistor-less relaxation oscillator for ultra-low power real-time clock applications.

Hiroki Asano, Tetsuya Hirose, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 0.1-0.6 V input range voltage boost converter with low-leakage driver for low-voltage energy harvesting.

Yuto Tsuji, Tetsuya Hirose, Toshihiro Ozaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

An ultra-low-power supercapacitor voltage monitoring system for low-voltage energy harvesting.

Takanori Sato, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems.

Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes.

Masanori Hashimoto, Ryo Shirai, Yuichi Itoh, Tetsuya Hirose

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Fully-Integrated High-Conversion-Ratio Dual-Output Voltage Boost Converter With MPPT for Low-Voltage Energy Harvesting.

Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa

IEEE J. Solid State Circuits, 2016

A Highly Efficient Switched-Capacitor Voltage Boost Converter with Nano-Watt MPPT Controller for Low-Voltage Energy Harvesting.

Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Image super-resolution with multi-channel convolutional neural networks.

Yu Kato, Shinya Ohtani, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A fully integrated, 1-µs start-up time, 32-MHz relaxation oscillator for low-power intermittent systems.

Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability.

Hiroki Asano, Tetsuya Hirose, Keishi Tsubaki, Taro Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

A 0.38-μW stand-by power, 50-nA-to-1-mA load current range DC-DC converter with self-biased linear regulator for ultra-low power battery management.

Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A 32-kHz Real-Time Clock Oscillator with On-Chip PVT Variation Compensation Circuit for Ultra-Low Power MCUs.

Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Electron., 2015

An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs.

Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation.

Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada

IEICE Electron. Express, 2015

A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs.

Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting.

Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters.

Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit.

Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Electron., 2014

A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis.

Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters.

Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the ESSCIRC 2014, 2014

2013

1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs.

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

IEEE J. Solid State Circuits, 2013

Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling.

Igors Homjakovs, Masanori Hashimoto, Tetsuya Hirose, Takao Onoye

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation.

Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto, Takao Onoye

IEICE Electron. Express, 2013

A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application.

Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

Proceedings of the ESSCIRC 2013, 2013

2012

A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs.

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

IEEE J. Solid State Circuits, 2012

Signal-dependent analog-to-digital converter based on MINIMAX sampling.

Igors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose

Proceedings of the International SoC Design Conference, 2012

A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator.

Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A low-power single-slope analog-to-digital converter with digital PVT calibration.

Yuji Osaki, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs.

Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique.

Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Electron., 2011

Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit.

Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Electron., 2011

A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs.

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

IEICE Electron. Express, 2011

Ultra-low power and low voltage circuit design for next-generation power-aware LSI applications.

Tetsuya Hirose

Proceedings of the International SoC Design Conference, 2011

A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs.

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 18.9-nA standby current comparator with adaptive bias current generator.

Kosuke Isono, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder.

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

A 1-muhboxW 600- hboxppm/^circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits.

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

IEEE Trans. Circuits Syst. II Express Briefs, 2010

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs.

Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

IEICE Trans. Electron., 2010

An Error Diagnosis Technique Based on Clustering of Elements.

Kosuke Shioki, Narumi Okada, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Super-resolution technique for thermography with dual-camera system.

Shingo Chikamatsu, Tomohiro Nakaya, Masakazu Kouda, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities.

Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs.

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

IEEE J. Solid State Circuits, 2009

Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques.

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits.

Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits.

Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic <i>V</i>_DDM control.

Kayoko Seto, Masaaki Iijima, Tetsuya Hirose, Masahiro Numa, Akira Tada, Takashi Ipposhi

IEICE Electron. Express, 2009

On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs.

Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs.

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

On Digital LSI Circuits Exploiting Collision-Based Fusion Gates.

Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya

Int. J. Unconv. Comput., 2008

Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution.

Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs.

Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

IEICE Electron. Express, 2008

A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits.

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

Proceedings of the ESSCIRC 2008, 2008

2007

CMOS Smart Sensor for Monitoring the Quality of Perishables.

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

IEEE J. Solid State Circuits, 2007

A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters.

Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya

Neurocomputing, 2007

A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors.

Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya

Int. J. Bifurc. Chaos, 2007

An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits.

Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs.

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning.

Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya

Proceedings of the International Joint Conference on Neural Networks, 2007

Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning.

Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya

Proceedings of the Neural Information Processing, 14th International Conference, 2007

2006

A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator.

Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya

Int. J. Bifurc. Chaos, 2006

A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy.

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Power-supply circuits for ultralow-power subthreshold MOS-LSIs.

Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

IEICE Electron. Express, 2006

2005

A quadrilateral-object composer for binary images with reaction-diffusion cellular automata.

Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya

Parallel Algorithms Appl., 2005

Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model.

Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya

Int. J. Unconv. Comput., 2005

Ultralow-Power Current Reference Circuit with Low Temperature Dependence.

Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya

IEICE Trans. Electron., 2005

A CMOS IF Variable Gain Amplifier with Exponential Gain Control.

Sungwoo Cha, Tetsuya Hirose, Masaki Haruoka, Toshimasa Matsuoka, Kenji Taniguchi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2004

Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata.

Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya

IEICE Electron. Express, 2004

A MOS circuit for bursting neural oscillators with excitable oregonators.

Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya

IEICE Electron. Express, 2004

Atomic configuration of boron pile-up at the Si/SiO2 interface.

Masayuki Furuhashi, Tetsuya Hirose, Hiroshi Tsuji, Masayuki Tachi, Kenji Taniguchi

IEICE Electron. Express, 2004

2000

A DSM Architecture for a Parallel Computer Cenju-4.

Takeo Hosomi, Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1999

Message Passing Communication in a Parallel Computer Cenju-4.

Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose, Takeo Hosomi, Hirokazu Takayama, Toshiyuki Nakata

Proceedings of the High Performance Computing, Second International Symposium, 1999

1995

Architecture of a parallel machine: Cenju-3.

Tsutomu Maruyama, Yasushi Kanoh, Tetsuya Hirose, Kazuhiro Muramatsu, Toshiyuki Nakata, Yoshihiro Asano, Yu Inamura

Syst. Comput. Jpn., 1995

1993

A Fine-Grained Parallel Genetic Algorithm for Distributed Parallel Systems.

Tsutomu Maruyama, Tetsuya Hirose, Akihiko Konagaya

Proceedings of the 5th International Conference on Genetic Algorithms, 1993