Shiann-Rong Kuang

According to our database1, Shiann-Rong Kuang authored at least 21 papers between 1993 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
Hardware Implementation of an Automatic Color Equalization Algorithm for Real-time Image Enhancement.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

2017
Design and implementation of a low-cost guided image filter for underwater image enhancement.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

2016
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support.
Proceedings of the VLSI Design, Automation and Test, 2015

2014
Efficient architecture and hardware implementation of hybrid fuzzy-Kalman filter for workload prediction.
Integr., 2014

2013
Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications.
J. Signal Process. Syst., 2013

Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

An exact method for estimating maximum errors of multi-mode floating-point iterative booth multiplier.
Int. J. Comput. Sci. Eng., 2013

Multiple-mode floating-point multiply-add fused unit for trading accuracy with power consumption.
Proceedings of the 2013 IEEE/ACIS 12th International Conference on Computer and Information Science, 2013

2011
High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Variable-Latency Floating-Point Multipliers for Low-Power Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Design of Power-Efficient Configurable Booth Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
Modified Booth Multipliers With a Regular Partial Product Array.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

2007
Design of power-efficient pipelined truncated multipliers with various output precision.
IET Comput. Digit. Tech., 2007

Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

2005
Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

2002
Design of a dynamic pipelined architecture for fuzzy color correction.
IEEE Trans. Very Large Scale Integr. Syst., 2002

1999
A New Pipelined Architecture for Fuzzy Color Correction.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1994
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Library-Adaptively Integrated Data Path Synthesis for DSP Systems.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


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