Yung-Chia Lin

According to our database, Yung-Chia Lin authored at least 14 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Guest Editorial: Special Issue on Systems Optimizations for DSP and AI Applications.

Kuan-Hsun Chen, Yung-Chia Lin, Jenq-Kuen Lee

J. Signal Process. Syst., May, 2023

2019

Guest Editorial: Special Issue on Embedded Multicore Applications and Optimization.

Yung-Chia Lin, Jenq-Kuen Lee, François Bodin

J. Signal Process. Syst., 2019

Case Study: Support OpenCL Complex Class for Baseband Computing.

Chia-Hsuan Chang, Chun-Chieh Yang, Jenq-Kuen Lee, Yung-Chia Lin

Proceedings of the International Workshop on OpenCL, 2019

2009

LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files.

Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee

Concurr. Comput. Pract. Exp., 2009

2008

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores.

Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee

J. Signal Process. Syst., 2008

Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch.

Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee

J. Signal Process. Syst., 2008

An MILP-based wire spreading algorithm for PSM-aware layout modification.

Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains.

Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang

J. Supercomput., 2007

PALF: compiler supports for irregular register files in clustered VLIW DSP processors.

Yung-Chia Lin, Yi-Ping You, Jenq Kuen Lee

Concurr. Comput. Pract. Exp., 2007

2006

Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors.

Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, Shih-Chang Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, Jenq Kuen Lee

Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006

2005

Compiler Supports and Optimizations for PAC VLIW DSP Processors.

Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, Jenq Kuen Lee

Proceedings of the Languages and Compilers for Parallel Computing, 2005

System-level design space exploration for security processor prototyping in analytical approaches.

Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Power-Aware Scheduling for Parallel Security Processors with Analytical Models.

Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang

Proceedings of the Languages and Compilers for High Performance Computing, 2004

2002

Compiler Optimizations with DSP-Specific Semantic Descriptions.

Yung-Chia Lin, Yuan-Shin Hwang, Jenq Kuen Lee

Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002