Ting-Chi Wang

Proceedings of the 2024 International Symposium on Physical Design, 2024

SMT-Based Layout Synthesis Approaches for Quantum Circuits.

[BibT_eX]

[DOI]

Zi-Hao Guo

Proceedings of the 2024 International Symposium on Physical Design, 2024

A Bounding Box-based Net Partitioning Method for Double-sided Routing.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

A Hybrid Approach to Reverse Engineering on Combinational Circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

An Effective Netlist Planning Approach for Double-sided Signal Routing.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

A Fast and Robust Global Router with Capacity Reduction Techniques.

[BibT_eX]

[DOI]

Yun-Kai Fang

Ye-Chih Lin

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

A Robust Routing Guide Generation Approach for Mixed-Size Designs.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Routability-aware Placement Guidance Generation for Mixed-size Designs.

[BibT_eX]

[DOI]

Chieh-Yu Cheng

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Fast and Accurate Detection of Audio Adversarial Examples.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Hybrid-Row-Height Design Placement Legalization Considering Cell Variants.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A Macro Legalization Approach Considering Minimum Channel Spacing and Buffer Area Reservation Constraints.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Generation of Black-box Audio Adversarial Examples Based on Gradient Approximation and Autoencoders.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

On Predicting Solution Quality of Maze Routing Using Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

HybridGP: Global Placement for Hybrid-Row-Height Designs.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs.

[BibT_eX]

[DOI]

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

2020

MiniDeviation: An Efficient Multi-Stage Bus-Aware Global Router.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

An Algorithm for Rule-based Layout Pattern Matching.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Forensic Artifacts of Network Traffic on WeChat Calls.

[BibT_eX]

[DOI]

Da-Yu Kao

Fu-Ching Tsai

Proceedings of the 22nd International Conference on Advanced Communication Technology, 2020

MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Audio Adversarial Examples Generation with Recurrent Neural Networks*.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

RDTA: An Efficient Routability-Driven Track Assignment Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

A Mixed-Height Standard Cell Placement Flow for Digital Circuit Blocks*.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A practical detailed placement algorithm under multi-cell spacing constraints.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

A routing framework for technology migration with bump encroachment.

[BibT_eX]

[DOI]

Integr., 2017

On refining standard cell placement for self-aligned double patterning.

[BibT_eX]

[DOI]

Ye-Hong Chen

Sheng-He Wang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Delay-driven layer assignment for advanced technology nodes.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Online slack-time binning for IO-registered die-to-die interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Negotiation-based track assignment considering local nets.

[BibT_eX]

[DOI]

Man-Pan Wong

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition.

[BibT_eX]

[DOI]

Tzu-Kai Chien

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

On Refining Row-Based Detailed Placement for Triple Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

2014

Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A study on unroutable placement recognition.

[BibT_eX]

[DOI]

Tzu-Kai Chien

Proceedings of the International Symposium on Physical Design, 2014

A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy.

[BibT_eX]

[DOI]

Zhen-Yu Peng

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A study on the use of parallel wiring techniques for sub-20nm designs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Metal layer planning for silicon interposers with consideration of routability and manufacturing cost.

[BibT_eX]

[DOI]

Tzu-Kai Chien

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Mask-cost-aware ECO routing∗.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Density-aware Detailed Placement with Instant Legalization.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs.

[BibT_eX]

[DOI]

Min-Sheng Chang

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Redundant-via-aware ECO routing.

[BibT_eX]

[DOI]

Hsi-An Chien

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement.

[BibT_eX]

[DOI]

Cha-Ru Li

Wai-Kei Mak

IEEE Trans. Very Large Scale Integr. Syst., 2013

An efficient hybrid synchronization technique for scalable multi-core instruction set simulations.

[BibT_eX]

[DOI]

Bo-Han Zeng

Ren-Song Tsay

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Pad Assignment for Die-Stacking System-in-Package Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

Through-Silicon Via Planning in 3-D Floorplanning.

[BibT_eX]

[DOI]

Ming-Chao Tsai

Ting Ting Hwang

IEEE Trans. Very Large Scale Integr. Syst., 2011

An enhanced global router with consideration of general layer directives.

[BibT_eX]

[DOI]

Yen-Jung Chang

Proceedings of the 2011 International Symposium on Physical Design, 2011

Simultaneous redundant via insertion and line end extension for yield optimization.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Optimal Double Via Insertion With On-Track Preference.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Enhanced Double Via Insertion Using Wire Bending.

[BibT_eX]

[DOI]

Shing-Tung Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

NTHU-Route 2.0: A Robust Global Router for Modern Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

GLADE: A modern global router considering layer directives.

[BibT_eX]

[DOI]

Yen-Jung Chang

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design.

[BibT_eX]

[DOI]

De-Yu Liu

Wai-Kei Mak

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Robust layer assignment for via optimization in multi-layer global routing.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Physical Design, 2009

Redundant via insertion with wire bending.

[BibT_eX]

[DOI]

Shing-Tung Lin

Proceedings of the 2009 International Symposium on Physical Design, 2009

2008

Slicing Floorplans.

[BibT_eX]

[DOI]

Martin D. F. Wong

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Congestion-Constrained Layer Assignment for Via Minimization in Global Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fast and Optimal Redundant Via Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Optimal post-routing redundant via insertion.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

NTHU-Route 2.0: a fast and stable global router.

[BibT_eX]

[DOI]

Yen-Jung Chang

Yu-Ting Lee

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A generalized network flow based algorithm for power-aware FPGA memory mapping.

[BibT_eX]

[DOI]

Tien-Yuan Hsu

Proceedings of the 45th Design Automation Conference, 2008

An MILP-based wire spreading algorithm for PSM-aware layout modification.

[BibT_eX]

[DOI]

Ming-Chao Tsai

Yung-Chia Lin

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

A new global router for modern designs.

[BibT_eX]

[DOI]

Jhih-Rong Gao

Pei-Ci Wu

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction.

[BibT_eX]

[DOI]

Pei-Ci Wu

Jhih-Rong Gao

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Buffered Delay Estimation Considering Process Variations.

[BibT_eX]

[DOI]

Tien-Ting Fang

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Post-routing redundant via insertion and line end extension with via density consideration.

[BibT_eX]

[DOI]

Kai-Yuan Chao

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Post-routing redundant via insertion for yield/reliability improvement.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Simple yet effective algorithms for block and I/O buffer placement in flip-chip design.

[BibT_eX]

[DOI]

Hao-Yueh Hsieh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Maze routing with OPC consideration.

[BibT_eX]

[DOI]

Yun-Ru Wu

Ming-Chao Tsai

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Concurrent flip-flop and buffer insertion with adaptive blockage avoidance.

[BibT_eX]

[DOI]

Zhong-Ching Lu

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Multilevel circuit clustering for delay minimization.

[BibT_eX]

[DOI]

Li-C. Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003

Optimal circuit clustering for delay minimization under a more general delay model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Performance-driven multi-level clustering for combinational circuits.

[BibT_eX]

[DOI]

Chin Ngai Sze

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Multi-Level Circuit Clustering for Delay Minimization.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Optimal circuit clustering with variable interconnect delay.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Module placement with pre-placed modules using the corner block list representation.

[BibT_eX]

[DOI]

S. Dhamdhere

Ningyu Zhou

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

Slicing floorplan design with boundary-constrained modules.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

Module placement with pre-placed modules using the B*-tree representation.

[BibT_eX]

[DOI]

Yi-He Jiang

Jianbang Lai

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Power minization in LUT-based FPGA technology mapping.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

Module placement with boundary constraints using the sequence-pair representation.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

On accelerating slicing floorplan design with boundary constraints.

[BibT_eX]

[DOI]

En-Cheng Liu

Tu-Hsing Lin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Feasible two-way circuit partitioning with complex resource constraints.

[BibT_eX]

[DOI]

Hsun-Cheng Lee

Proceedings of ASP-DAC 2000, 2000

1999

Faster and Better Spectral Algorithms for Multi-Way Partitioning.

[BibT_eX]

[DOI]

Jan-Yang Chang

Yu-Chen Liu

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997

Routing for symmetric FPGAs and FPICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1995

Optimal net assignment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Performance-driven channel pin assignment algorithms.

[BibT_eX]

[DOI]

T. W. Her

Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1993

Graph-based techniques to speed up floorplan area optimization.

[BibT_eX]

[DOI]

Integr., 1993

A Graph Partitioning Problem for Multiple-chip Design.

[BibT_eX]

Yao-Ping Chen

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

On over-the-cell channel routing.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

A note on the Complexity of Stockmeyer's floorplan Optimization Technique.

[BibT_eX]

[DOI]

Proceedings of the Algorithmic Aspects of VLSI Layout, 1993

1992

Optimal floorplan area optimization.

[BibT_eX]

[DOI]

Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

A Graph Theoretic Technique to Speed up Floorplan Area Optimization.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

Efficient shape curve construction in floorplan design.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1991

1990

An Optimal Algorithm for Floorplan Area Optimization.

[BibT_eX]

[DOI]