Yi-Ping You

Orcid: 0000-0002-4455-3147

According to our database1, Yi-Ping You authored at least 29 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.



In proceedings 
PhD thesis 


Online presence:

On csauthors.net:


DLOOPT: An Optimization Assistant on AutoTVM for Deep Learning Operators.
J. Signal Process. Syst., May, 2023

Mapping-Free GPU Offloading in OpenMP Using Unified Memory.
Proceedings of the 52nd International Conference on Parallel Processing Workshops, 2023

Reduced O3 subsequence labelling: a stepping stone towards optimisation sequence prediction.
Connect. Sci., 2022

Profile-guided optimisation for indirect branches in a binary translator.
Connect. Sci., 2022

Offworker: An Offloading Framework for Parallel Web Applications.
Proceedings of the Web Information Systems Engineering - WISE 2022, 2022

Structured Concurrency: A Review.
Proceedings of the Workshop Proceedings of the 51st International Conference on Parallel Processing, 2022

CLPKM: A checkpoint-based preemptive multitasking framework for OpenCL kernels.
J. Syst. Archit., 2019

Translating AArch64 Floating-Point Instruction Set to the x86-64 Platform.
Proceedings of the 48th International Conference on Parallel Processing, 2019

Enabling OpenCL Preemptive Multitasking Using Software Checkpointing.
Proceedings of the 47th International Conference on Parallel Processing, 2018

VecRA: A Vector-Aware Register Allocator for GPU Shader Processors.
ACM Trans. Embed. Comput. Syst., 2016

A static region-based compiler for the Dalvik virtual machine.
Softw. Pract. Exp., 2016

VirtCL: a framework for OpenCL device abstraction and management.
Proceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2015

Vector-aware register allocation for GPU shader processors.
Proceedings of the 2015 International Conference on Compilers, 2015

Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs.
ACM Trans. Design Autom. Electr. Syst., 2014

Enabling OpenCL support for GPGPU in Kernel-based Virtual Machine.
Softw. Pract. Exp., 2014

Energy-aware code motion for GPU shader processors.
ACM Trans. Embed. Comput. Syst., 2013

LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files.
Concurr. Comput. Pract. Exp., 2009

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores.
J. Signal Process. Syst., 2008

Compilation for compact power-gating controls.
ACM Trans. Design Autom. Electr. Syst., 2007

Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains.
J. Supercomput., 2007

PALF: compiler supports for irregular register files in clustered VLIW DSP processors.
Concurr. Comput. Pract. Exp., 2007

Enabling compiler flow for embedded VLIW DSP processors with distributed register files.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Compilers for leakage power reduction.
ACM Trans. Design Autom. Electr. Syst., 2006

Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors.
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006

Compiler Supports and Optimizations for PAC VLIW DSP Processors.
Proceedings of the Languages and Compilers for Parallel Computing, 2005

A sink-n-hoist framework for leakage power reduction.
Proceedings of the EMSOFT 2005, 2005

Low-power techniques for network security processors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Power-Aware Scheduling for Parallel Security Processors with Analytical Models.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors.
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002