Yuta Nagahara

Orcid: 0009-0007-8390-6164

According to our database1, Yuta Nagahara authored at least 5 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
DMSA: An Efficient Architecture for Sparse-Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow.
IEEE Trans. Very Large Scale Integr. Syst., July, 2025

BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

2024
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024

Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
Decision Forest Training Accelerator Based on Binary Feature Decomposition.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023


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