Masato Motomura
Orcid: 0000-0003-1543-1252
According to our database1,
Masato Motomura
authored at least 116 papers
between 1994 and 2024.
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Bibliography
2024
CoRR, 2024
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.
IEEE Access, 2024
IEEE Access, 2024
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization.
IEEE Access, 2024
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
2023
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems.
IEICE Trans. Inf. Syst., December, 2023
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2023
2022
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers.
IEICE Trans. Inf. Syst., December, 2022
IEEE Trans. Circuits Syst. Video Technol., 2022
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the International Conference on Machine Learning, 2022
Ring-VCO-based ReLU activation function with linearity improvement for pulsed neuron circuits.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions.
IEEE J. Solid State Circuits, 2021
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation.
Int. J. Netw. Comput., 2021
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training.
Int. J. Netw. Comput., 2021
Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture.
IEEE Access, 2021
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning.
Proceedings of the International Conference on Field-Programmable Technology, 2021
Proceedings of the 32nd British Machine Vision Conference 2021, 2021
2020
IEEE Trans. Circuits Syst. Video Technol., 2020
Int. J. Netw. Comput., 2020
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation.
Proceedings of the Eighth International Symposium on Computing and Networking, 2020
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training.
Proceedings of the Eighth International Symposium on Computing and Networking, 2020
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
2019
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.
IEEE J. Solid State Circuits, 2019
Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2019
IEICE Trans. Inf. Syst., 2019
IEICE Trans. Inf. Syst., 2019
A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators.
Proceedings of the 2019 Seventh International Symposium on Computing and Networking, 2019
Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band.
Proceedings of the 2019 Digital Image Computing: Techniques and Applications, 2019
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019
2018
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA.
Microprocess. Microsystems, 2018
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.
IEEE J. Solid State Circuits, 2018
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing.
Complex., 2018
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the IEEE Visual Communications and Image Processing, 2018
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
Proceedings of the Principles and Structures of FPGAs., 2018
2017
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the Artificial Intelligence XXXIV, 2017
In-memory area-efficient signal streaming processor design for binary neural networks.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the Fifth International Symposium on Computing and Networking, 2017
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017
2016
IEEE J. Solid State Circuits, 2016
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata.
Int. J. Unconv. Comput., 2016
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
IEEE J. Solid State Circuits, 2015
J. Inf. Process., 2015
IEICE Trans. Electron., 2015
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
IEICE Electron. Express, 2014
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Proceedings of the International Conference on High Performance Computing & Simulation, 2013
Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013
2011
ACM Trans. Reconfigurable Technol. Syst., 2011
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Panel discussions: Impact on society by fusion and harmony of mobile devices, servers, and networks - Their direction of evolutions and optimal roles.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Computers, 2004
Wrapper-based bus implementation techniques for performance improvement and cost reduction.
IEEE J. Solid State Circuits, 2004
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004
2003
New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic.
J. Syst. Archit., 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
A New Reconfigurable Hardware Architecture for High Throughput Networking Applications and its Design Methodology.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
A New Hardware Algorithm for Fast IP Routing Targeting Programmable Routers.
Proceedings of the Network Control and Engineering for QoS, 2003
2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk.
Proceedings of ASP-DAC 2000, 2000
1998
IEEE J. Solid State Circuits, 1998
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998
1995
IEEE J. Solid State Circuits, April, 1995
Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995
1994
IEEE J. Solid State Circuits, March, 1994