Kazushi Kawamura
Orcid: 0000-0002-0795-2974
According to our database1,
Kazushi Kawamura
authored at least 44 papers
between 2013 and 2024.
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Bibliography
2024
CoRR, 2024
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.
IEEE Access, 2024
IEEE Access, 2024
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization.
IEEE Access, 2024
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
2023
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems.
IEICE Trans. Inf. Syst., December, 2023
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2023
2022
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers.
IEICE Trans. Inf. Syst., December, 2022
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the International Conference on Machine Learning, 2022
2021
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions.
IEEE J. Solid State Circuits, 2021
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation.
Int. J. Netw. Comput., 2021
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training.
Int. J. Netw. Comput., 2021
Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations.
IEICE Trans. Inf. Syst., 2021
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning.
Proceedings of the International Conference on Field-Programmable Technology, 2021
2020
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation.
Proceedings of the Eighth International Symposium on Computing and Networking, 2020
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training.
Proceedings of the Eighth International Symposium on Computing and Networking, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
IPSJ Trans. Syst. LSI Des. Methodol., 2019
Proceedings of the International Conference on Field-Programmable Technology, 2019
Mapping Constrained Slot-Placement Problems to Ising Models and its Evaluations by an Ising Machine.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
2018
A loop structure optimization targeting high-level synthesis of fast number theoretic transform.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Proceedings of the International SoC Design Conference, 2017
2016
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the International SoC Design Conference, 2016
2015
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 10th Asian Control Conference, 2015
2014
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
A partial redundant fault-secure high-level synthesis algorithm for RDR architectures.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013