According to our database1, Yuzheng Ding
Legend:Book In proceedings Article PhD thesis Other
FPGA Technology Mapping.
Encyclopedia of Algorithms, 2016
FPGA Technology Mapping.
Proceedings of the Encyclopedia of Algorithms, 2008
The effect of post-layout pin permutation on timing.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
Incremental physical resynthesis for timing optimization.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999
Combinational logic synthesis for LUT based field programmable gate arrays.
ACM Trans. Design Autom. Electr. Syst., 1996
RASP: A General Logic Synthesis System for SRAM-Based FPGAs.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996
On Nominal Delay Minimization in LUT-based FPGA Technology Mapping.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995
On area/depth trade-off in LUT-based FPGA technology mapping.
IEEE Trans. VLSI Syst., 1994
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994
On the Complexity of Building an Interval Heap.
Inf. Process. Lett., 1994
On nominal delay minimization in LUT-based FPGA technology mapping.
LUT-based FPGA technology mapping under arbitrary net-delay models.
Computers & Graphics, 1994
The Relaxed min-max Heap.
Acta Inf., 1993
The K-D Heap: An Efficient Multi-dimensional Priority Queue.
Proceedings of the Algorithms and Data Structures, Third Workshop, 1993
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping.
Proceedings of the 30th Design Automation Conference. Dallas, 1993
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.
IEEE Design & Test of Computers, 1992
Best case lower bounds for Heapsort.
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992