Yuzheng Ding

According to our database1, Yuzheng Ding authored at least 19 papers between 1992 and 2016.

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Bibliography

2016
FPGA Technology Mapping.
Encyclopedia of Algorithms, 2016

2008
FPGA Technology Mapping.
Proceedings of the Encyclopedia of Algorithms, 2008

2005
The effect of post-layout pin permutation on timing.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
Incremental physical resynthesis for timing optimization.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

1999
Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1996
Combinational logic synthesis for LUT based field programmable gate arrays.
ACM Trans. Design Autom. Electr. Syst., 1996

RASP: A General Logic Synthesis System for SRAM-Based FPGAs.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

1995
On Nominal Delay Minimization in LUT-based FPGA Technology Mapping.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

On the Complexity of Building an Interval Heap.
Inf. Process. Lett., 1994

LUT-based FPGA technology mapping under arbitrary net-delay models.
Computers & Graphics, 1994

1993
The Relaxed min-max Heap.
Acta Inf., 1993

The K-D Heap: An Efficient Multi-dimensional Priority Queue.
Proceedings of the Algorithms and Data Structures, Third Workshop, 1993

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.
IEEE Design & Test of Computers, 1992

Best case lower bounds for Heapsort.
Computing, 1992

An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992


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