Yuzheng Ding

According to our database, Yuzheng Ding authored at least 19 papers between 1992 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

FPGA Technology Mapping.

Jason Cong, Yuzheng Ding

Encyclopedia of Algorithms, 2016

2008

FPGA Technology Mapping.

Jason Cong, Yuzheng Ding

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

2005

The effect of post-layout pin permutation on timing.

Yuzheng Ding, Peter Suaris, Nan-Chi Chou

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

Incremental physical resynthesis for timing optimization.

Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

1999

Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.

Jason Cong, Chang Wu, Yuzheng Ding

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1996

Combinational logic synthesis for LUT based field programmable gate arrays.

Jason Cong, Yuzheng Ding

ACM Trans. Design Autom. Electr. Syst., 1996

RASP: A General Logic Synthesis System for SRAM-Based FPGAs.

Jason Cong, John Peck, Yuzheng Ding

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

1994

On area/depth trade-off in LUT-based FPGA technology mapping.

Jason Cong, Yuzheng Ding

IEEE Trans. Very Large Scale Integr. Syst., 1994

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.

Jason Cong, Yuzheng Ding

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

On the Complexity of Building an Interval Heap.

Yuzheng Ding, Mark Allen Weiss

Inf. Process. Lett., 1994

On nominal delay minimization in LUT-based FPGA technology mapping.

Jason Cong, Yuzheng Ding

Integr., 1994

LUT-based FPGA technology mapping under arbitrary net-delay models.

Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen

Comput. Graph., 1994

1993

The Relaxed min-max Heap.

Yuzheng Ding, Mark Allen Weiss

Acta Informatica, 1993

The K-D Heap: An Efficient Multi-dimensional Priority Queue.

Yuzheng Ding, Mark Allen Weiss

Proceedings of the Algorithms and Data Structures, Third Workshop, 1993

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.

Jason Cong, Yuzheng Ding

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.

Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar

IEEE Des. Test Comput., 1992

Best case lower bounds for Heapsort.

Yuzheng Ding, Mark Allen Weiss

Computing, 1992

An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization.

Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.

Jason Cong, Yuzheng Ding

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992