Kuang-Chien Chen

Proceedings of the 2005 Design, 2005

2004

A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation.

[BibT_eX]

[DOI]

Chia-Chih Yen

Jing-Yang Jou

IEEE Des. Test Comput., 2004

2002

A Practical Approach to Cycle Bound Estimation for Property Checking.

[BibT_eX]

Chia-Chih Yen

Jing-Yang Jou

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

2001

Verifying sequential equivalence using ATPG techniques.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2001

2000

AQUILA: An Equivalence Checking System for Large Sequential Designs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

1999

Logic synthesis for engineering change.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

AutoFix: a hybrid tool for automatic logic rectification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998

Cost-free scan: a low-overhead scan path design.

[BibT_eX]

[DOI]

Mike Tien-Chien Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Fault-Simulation Based Design Error Diagnosis for Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

1997

Incremental logic rectification.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

AQUILA: An equivalence verifier for large sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

An ATPG-Based Framework for Verifying Sequential Equivalence.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

A novel methodology for transistor-level power estimation.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

On Verifying the Correctness of Retimed Circuits.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Sequential Permissible Functions and their Application to Circuit Optimization.

[BibT_eX]

[DOI]

Mike Tien-Chien Lee

Proceedings of the 1996 European Design and Test Conference, 1996

Compact Vector Generation for Accurate Power Simulation.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

Error Correction Based on Verification Techniques.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Re-engineering of timing constrained placements for regular architectures.

[BibT_eX]

[DOI]

Anmol Mathur

C. L. Liu

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Cost-free scan: a low-overhead scan path design methodology.

[BibT_eX]

[DOI]

Mike Tien-Chien Lee

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs.

[BibT_eX]

[DOI]

Anmol Mathur

C. L. Liu

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

Logic Synthesis for Engineering Change.

[BibT_eX]

[DOI]

Shih-Chieh Chang

Proceedings of the 32st Conference on Design Automation, 1995

Logic rectification and synthesis for engineering change.

[BibT_eX]

[DOI]

David Ihsin Cheng

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

LUT-based FPGA technology mapping under arbitrary net-delay models.

[BibT_eX]

[DOI]

Comput. Graph., 1994

1993

A performance driven hierarchical partitioning placement algorithm.

[BibT_eX]

[DOI]

Tong Gao

Chung Laung (Dave) Liu

Proceedings of the European Design Automation Conference 1993, 1993

Boolean matching based on Boolean unification.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

1992

DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1992

An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Maximal reduction of lookup-table based FPGAs.

[BibT_eX]

[DOI]

Jason Cong

Proceedings of the conference on European design automation, 1992

Efficient Sum-to-One Subsets Algorithm for Logic Optimization.

[BibT_eX]

[DOI]

Masahiro Fujita

Proceedings of the 29th Design Automation Conference, 1992

1991

Logic synthesis and optimization algorithms

[BibT_eX]

[DOI]

PhD thesis, 1991

Concurrent Resynthesis for Network Optimization.

[BibT_eX]

[DOI]

Masahiro Fujita

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Application of Boolean Unification to Combinational Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Resynthesis Approach for Network Optimization.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

1990

Timing Optimization for Multi-Level Combinational Networks.

[BibT_eX]

[DOI]

Saburo Muroga

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

SYLON-DREAM: a multi-level network synthesizer.

[BibT_eX]

[DOI]

Saburo Muroga

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988

Input assignment algorithm for decoded-PLAs with multi-input decoders.

[BibT_eX]

[DOI]