Zerun Li

Orcid: 0000-0002-7672-0667

According to our database1, Zerun Li authored at least 19 papers between 2018 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing.
IEEE Trans. Computers, April, 2025

Conjunction subspaces test for conformal and selective classification.
Inf. Sci., 2025

Statistical significance of cluster membership for categorical data.
Eng. Appl. Artif. Intell., 2025

In-Memory Computing Accelerator for Iterative Linear Algebra Solvers.
IEEE Comput. Archit. Lett., 2025

CIM-BLAS: Computing-in-Memory Accelerator for BLAS.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024
Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators.
IEEE Des. Test, October, 2024

GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication.
IEEE Trans. Computers, June, 2024

TMiner: A Vertex-Based Task Scheduling Architecture for Graph Pattern Mining.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

2023
FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

FSPA: An FeFET-based Sparse Matrix-Dense Vector Multiplication Accelerator.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Automatic Modulation Classification for MASK, MPSK, and MQAM Signals Based on Hierarchical Self-Organizing Map.
Sensors, 2022

Convolutional Neural Network Accelerator for Compression Based on Simon k-means.
Proceedings of the International Joint Conference on Neural Networks, 2022

GraphRing: an HMC-ring based graph processing framework with optimized data movement.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes.
Symmetry, 2021

Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph.
IEEE Access, 2021

2020
Practical AMC model based on SAE with various optimisation methods under different noise environments.
IET Commun., 2020

2018
A task-based multi-core allocation mechanism for packet acceleration.
IEICE Electron. Express, 2018

A Novel Priority-Allocated Scheme for Flow-Based Queue Managers.
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018


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