Xiaowen Chen

According to our database1, Xiaowen Chen authored at least 47 papers between 2001 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition.
IEEE Trans. VLSI Syst., 2018

VP-Router: On balancing the traffic load in on-chip networks.
IEICE Electronic Express, 2018

Cache Access Fairness in 3D Mesh-Based NUCA.
IEEE Access, 2018

Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems.
ACM Trans. Embedded Comput. Syst., 2017

Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop.
IEICE Electronic Express, 2017

A novel power-efficient IC test scheme.
IEICE Electronic Express, 2017

Fairness-oriented switch allocation for networks-on-chip.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Fairness-Oriented and Location-Aware NUCA for Many-Core SoC.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Design and implementation of high-speed configurable ECC co-processor.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Iteration Interleaving-Based SIMD Lane Partition.
TACO, 2016

Multi-bit transient fault control for NoC links using 2D fault coding method.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.
JSW, 2015

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.
J. Electrical and Computer Engineering, 2015

Identifying novel associations between small molecules and miRNAs based on integrated molecular networks.
Bioinformatics, 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Coupled Model of the 1D River Network and 3D Estuary Based on Hydrodynamics and Suspended Sediment Simulation.
J. Applied Mathematics, 2014

Numerical Simulation of Flow and Suspended Sediment Transport in the Distributary Channel Networks.
J. Applied Mathematics, 2014

Round-trip latency prediction for memory access fairness in mesh-based many-core architectures.
IEICE Electronic Express, 2014

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.
IEICE Electronic Express, 2014

Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.
Computers & Electrical Engineering, 2013

Identification of active transcription factor and miRNA regulatory pathways in Alzheimer's disease.
Bioinformatics, 2013

CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors.
IEICE Electronic Express, 2012

Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures.
Computer Architecture Letters, 2012

Dissection of human MiRNA regulatory influence to subpathway.
Briefings in Bioinformatics, 2012

Multi-scale Segmentation Algorithm Parameters Optimization Based on Evolutionary Computation.
Proceedings of the Computational Intelligence and Intelligent Systems, 2012

Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Hybrid Distributed Shared Memory Space in Multi-core Processors.
JSW, 2011

Cooperative communication based barrier synchronization in on-chip mesh architectures.
IEICE Electronic Express, 2011

DSBS: Distributed and Scalable Barrier Synchronization in Many-Core Network-on-Chips.
Proceedings of the IEEE 10th International Conference on Trust, 2011

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Design and chip implementation of a heterogeneous multi-core DSP.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP.
J. Comput. Sci. Technol., 2010

Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Multiple Search Centers Based Fast Motion Estimation Algorithm for H.264/AVC.
Proceedings of the 2010 International Conference on Parallel and Distributed Computing, 2010

Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips.
Proceedings of the Third International Symposium on Parallel Architectures, 2010

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Scalability of weak consistency in NoC based multicore architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform.
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010

Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller.
Proceedings of the Design, Automation and Test in Europe, 2010

Scalability of relaxed consistency models in NoC based multicore architectures.
SIGARCH Computer Architecture News, 2009

Enhanced piecewise regression based on deterministic annealing.
Science in China Series F: Information Sciences, 2008

FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs.
Proceedings of the Advances in Computer Systems Architecture, 2007

A graphical user interface for executing formal specifications.
Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), 2001