Xiaowen Chen
Orcid: 0000-0002-4029-1805
According to our database1,
Xiaowen Chen
authored at least 66 papers
between 2001 and 2022.
Collaborative distances:
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Bibliography
2022
Towards Convolutional Neural Network Acceleration and Compression Based on Simonk-Means.
Sensors, 2022
Proceedings of the International Joint Conference on Neural Networks, 2022
Proceedings of the Neural Information Processing - 29th International Conference, 2022
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022
2021
Research on Image Retrieval Algorithm Based on Combination of Color and Shape Features.
J. Signal Process. Syst., 2021
EURASIP J. Wirel. Commun. Netw., 2021
Systematical identification of cell-specificity of CTCF-gene binding based on epigenetic modifications.
Briefings Bioinform., 2021
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021
2020
Global Analysis of Gene Expression Profiles Provides Novel Insights into the Development and Evolution of the Large Crustacean <i>Eriocheir sinensis</i>.
Genom. Proteom. Bioinform., 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
A Research and Design of Lightweight Convolutional Neural Networks Accelerator Based on Systolic Array Structure.
Proceedings of the ICRAI 2020: 6th International Conference on Robotics and Artificial Intelligence, 2020
Middle-School Chinese Students Adjusting to Western Approaches to Teaching and Learning: A Study of Students' Intercultural Competence.
Proceedings of the Interdisciplinarity in the Learning Sciences: Proceedings of the 14th International Conference of the Learning Sciences, 2020
Proceedings of the ICCTA 2020: 6th International Conference on Computer and Technology Applications, 2020
2019
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEICE Electron. Express, 2018
2017
ACM Trans. Embed. Comput. Syst., 2017
IEICE Electron. Express, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
ACM Trans. Archit. Code Optim., 2016
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
2015
Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.
J. Softw., 2015
Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.
J. Electr. Comput. Eng., 2015
Identifying novel associations between small molecules and miRNAs based on integrated molecular networks.
Bioinform., 2015
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2014
A Coupled Model of the 1D River Network and 3D Estuary Based on Hydrodynamics and Suspended Sediment Simulation.
J. Appl. Math., 2014
Numerical Simulation of Flow and Suspended Sediment Transport in the Distributary Channel Networks.
J. Appl. Math., 2014
Round-trip latency prediction for memory access fairness in mesh-based many-core architectures.
IEICE Electron. Express, 2014
Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.
IEICE Electron. Express, 2014
2013
Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.
Comput. Electr. Eng., 2013
Identification of active transcription factor and miRNA regulatory pathways in Alzheimer's disease.
Bioinform., 2013
2012
CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors.
IEICE Electron. Express, 2012
IEEE Comput. Archit. Lett., 2012
Briefings Bioinform., 2012
Multi-scale Segmentation Algorithm Parameters Optimization Based on Evolutionary Computation.
Proceedings of the Computational Intelligence and Intelligent Systems, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
2011
Cooperative communication based barrier synchronization in on-chip mesh architectures.
IEICE Electron. Express, 2011
DSBS: Distributed and Scalable Barrier Synchronization in Many-Core Network-on-Chips.
Proceedings of the IEEE 10th International Conference on Trust, 2011
Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
J. Comput. Sci. Technol., 2010
Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the 2010 International Conference on Parallel and Distributed Computing, 2010
Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips.
Proceedings of the Third International Symposium on Parallel Architectures, 2010
Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
SIGARCH Comput. Archit. News, 2009
2008
Sci. China Ser. F Inf. Sci., 2008
2007
Proceedings of the Advances in Computer Systems Architecture, 2007
2001
Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), 2001