Zeyad Aklah

According to our database, Zeyad Aklah authored at least 8 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA.

Ehsan Kabir, Arpan Poudel, Zeyad Aklah, Miaoqing Huang, David Andrews

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2022

2021

FPGA-Based Implementation of MSPWM Utilizing 6-Input LUT for Reference Signal Generation.

Amean Al Safi, Ali S. Al-Khayyat, Zeyad Aklah

Proceedings of the 11th IEEE Annual Computing and Communication Workshop and Conference, 2021

2016

A hardware/software prototyping system for driving assistance investigations.

Jakob Anders, Michael Mefenza, Christophe Bobda, Franck Yonga, Zeyad Aklah, Kevin Gunn

J. Real Time Image Process., 2016

A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators.

Zeyad Aklah, Sen Ma, David Andrews

CoRR, 2016

Just In Time Assembly of Accelerators.

Sen Ma, Zeyad Aklah, David Andrews

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Run time interpretation for creating custom accelerators.

Sen Ma, Zeyad Aklah, David Andrews

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

A run time interpretation approach for creating custom accelerators.

Sen Ma, Zeyad Aklah, David Andrews

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A Flexible Multilayer Perceptron Co-processor for FPGAs.

Zeyad Aklah, David Andrews

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015