Zeyad Aklah

Orcid: 0000-0002-5617-8946

According to our database1, Zeyad Aklah authored at least 9 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Fall Detection in Q-eBall.
Dataset, May, 2024

2022
A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2022

2021
FPGA-Based Implementation of MSPWM Utilizing 6-Input LUT for Reference Signal Generation.
Proceedings of the 11th IEEE Annual Computing and Communication Workshop and Conference, 2021

2016
A hardware/software prototyping system for driving assistance investigations.
J. Real Time Image Process., 2016

A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators.
CoRR, 2016

Just In Time Assembly of Accelerators.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Run time interpretation for creating custom accelerators.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A run time interpretation approach for creating custom accelerators.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A Flexible Multilayer Perceptron Co-processor for FPGAs.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015


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