Christophe Bobda

Orcid: 0000-0002-9042-9470

According to our database1, Christophe Bobda authored at least 179 papers between 2000 and 2024.

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Bibliography

2024
Programmable EM Sensor Array for Golden-Model Free Run-time Trojan Detection and Localization.
CoRR, 2024

ISO-TENANT: Rethinking FPGA Power Distribution Network (PDN): A Hardware Based Solution for Remote Power Side Channel Attacks in FPGA.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023
Semi-Supervised Image Stitching from Unstructured Camera Arrays.
Sensors, December, 2023

SeRO: Self-Supervised Reinforcement Learning for Recovery from Out-of-Distribution Situations.
Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence, 2023

OpenTitan based Multi-Level Security in FPGA System-on-Chips.
Proceedings of the International Conference on Field Programmable Technology, 2023

A Tenant Side Compilation Solution for Cloud FPGA Deployment.
Proceedings of the International Conference on Field Programmable Technology, 2023

2022
Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure.
ACM Trans. Reconfigurable Technol. Syst., 2022

The Future of FPGA Acceleration in Datacenters and the Cloud.
ACM Trans. Reconfigurable Technol. Syst., 2022

Event camera simulator design for modeling attention-based inference architectures.
J. Real Time Image Process., 2022

Towards a component-based acceleration of convolutional neural networks on FPGAs.
J. Parallel Distributed Comput., 2022

TrustToken, a Trusted SoC solution for Non-Trusted Intellectual Property (IP)s.
CoRR, 2022

Multi-Tenant Cloud FPGA: A Survey on Security.
CoRR, 2022

Trusted IP Solution in Multi-tenant Cloud FPGA Platform.
Proceedings of the 8th IEEE World Forum on Internet of Things, 2022

Coarse-Grained Floorplanning for streaming CNN applications on Multi-Die FPGAs.
Proceedings of the 21st International Symposium on Parallel and Distributed Computing, 2022

Accelerating Hybrid Quantized Neural Networks on Multi-tenant Cloud FPGA.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Metrics for Assessing Security of System-on-Chip.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021
Towards an Efficient CNN Inference Architecture Enabling In-Sensor Processing.
Sensors, 2021

HARP: Hierarchical Attention Oriented Region-Based Processing for High-Performance Computation in Vision Sensor.
Sensors, 2021

Bio-inspired smart vision sensor: toward a reconfigurable hardware modeling of the hierarchical processing in the brain.
J. Real Time Image Process., 2021

Performance Exploration of Virtualization Systems.
CoRR, 2021

A Security Architecture for Domain Isolation in Multi-Tenant Cloud FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Performance Study of Multi-tenant Cloud FPGAs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

Exploring a Layer-based Pre-implemented Flow for Mapping CNN on FPGA.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

Domain Isolation in FPGA-Accelerated Cloud and Data Center Applications.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

ESCA: Event-Based Split-CNN Architecture with Data-Level Parallelism on UltraScale+ FPGA.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
Hierarchical Design of a Secure Image Sensor with Dynamic Reconfiguration.
J. Signal Process. Syst., 2020

MeXT-SE: A Design Tool to Transparently Generate Secure MPSoC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

IoT Device security through dynamic hardware isolation with cloud-Based update.
J. Syst. Archit., 2020

Internet of smart-cameras for traffic lights optimization in smart cities.
Internet Things, 2020

Large Common Plansets-4-Points Congruent Sets for Point Cloud Registration.
ISPRS Int. J. Geo Inf., 2020

Decentralised indoor smart camera mapping and hierarchical navigation for autonomous ground vehicles.
IET Comput. Vis., 2020

Performance Exploration on Pre-implemented CNN Hardware Accelerator on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2020

Near-Sensor Inference Architecture with Region Aware Processing.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

MeXT-SE: A System-Level Design Tool to Transparently Generate Secure MPSoC.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Accommodating Multi-Tenant FPGAs in the Cloud.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Late Breaking Results: Automated Hardware Generation of CNN Models on FPGAs.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2020

FPGA Accelerated Embedded System Security Through Hardware Isolation.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020

Architecture Support for FPGA Multi-tenancy in the Cloud.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
Introduction to the Special Section on Security in FPGA-accelerated Cloud and Datacenters.
ACM Trans. Reconfigurable Technol. Syst., 2019

Neuromorphic Image Sensor Design with Region-Aware Processing.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Reconfigurable Layered-Based Bio-Inspired Smart Image Sensor.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Automatic Generation of Application-Specific FPGA Overlays with RapidWright.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Automatic Assessment of Infant Sleep Safety Using Semantic Segmentation.
Proceedings of the 13th International Conference on Distributed Smart Cameras, 2019

From PC2BIM: Automatic Model generation from Indoor Point Cloud.
Proceedings of the 13th International Conference on Distributed Smart Cameras, 2019

Automatic Generation of Waypoint Graphs from Distributed Ceiling-Mounted Smart Cameras for Decentralized Multi-Robot Indoor Navigation.
Proceedings of the 13th International Conference on Distributed Smart Cameras, 2019

Synthesis of Hardware Sandboxes for Trojan Mitigation in Systems on Chip.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

MeXT: A Flow for Multiprocessor Exploration.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

Visual Cortex Inspired Pixel-Level Re-configurable Processors for Smart Image Sensors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A distributed smart camera apparatus to enable scene immersion: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

Automatic Generation of Application-Specific FPGA Overlays.
Proceedings of the 2019 International Conference on Compliers, 2019

Event-Based Re-configurable Hierarchical Processors for Smart Image Sensors.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Component interconnect and data access interface for embedded vision applications.
J. Real Time Image Process., 2018

High-level synthesis of on-chip multiprocessor architectures based on answer set programming.
J. Parallel Distributed Comput., 2018

Pixel-Parallel Architecture for Neuromorphic Smart Image Sensor with Visual Attention.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Enhancing Lifetime of PCM-Based Main Memory with Efficient Recovery of Stuck-at Faults.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

R-Covnet: Recurrent Neural Convolution Network for 3D Object Recognition.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

FPGA Virtualization in Cloud-Based Infrastructures Over Virtio.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

FLexiTASK: A Flexible FPGA Overlay for Efficient Multitasking.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube Computers.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Secure Hardware Kernels Execution in CPU+FPGA Heterogeneous Cloud.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Inheriting Software Security Policies within Hardware IP Components.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Design of a Reconfigurable 3D Pixel-Parallel Neuromorphic Architecture for Smart Image Sensor.
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2018

FPGAVirt: A Novel Virtualization Framework for FPGAs in the Cloud.
Proceedings of the 11th IEEE International Conference on Cloud Computing, 2018

2017
CAPSL: The Component Authentication Process for Sandboxed Layouts.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A System on FPGA for Fast Handwritten Digit Recognition in Embedded Smart Cameras.
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017

SoC Design Of A Novel Cluster-Based Approach for Real-Time Lane Detection in Low Quality Images.
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017

Synthesis of hardware sandboxes for Trojan mitigation in systems on chip.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Shielding non-trusted IPs in SoCs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Automatic Generation of Hardware Sandboxes for Trojan Mitigation in Systems on Chip (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

CAPSL: A Tool for Automatic Generation of Hardware Sandboxes for IP Security.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Applying the Flask Security Architecture to Secure SoC Design.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Towards the application of flask security architecture to SoC design: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

Secure integration of non-trusted IPs in SoCs.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Efficient network clustering for traffic reduction in embedded smart camera networks.
J. Real Time Image Process., 2016

A hardware/software prototyping system for driving assistance investigations.
J. Real Time Image Process., 2016

Hardware/Software Isolation and Protection Architecture for Transparent Security Enforcement in Networked Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Sparsely connected neural networks in FPGA for handwritten digit recognition.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Vision-Based Path Construction and Maintenance for Indoor Guidance of Autonomous Ground Vehicles Based on Collaborative Smart Cameras.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

Defeating drone jamming with hardware sandboxing.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Automatic Assessment of Environmental Hazards for Fall Prevention Using Smart-Cameras.
Proceedings of the First IEEE International Conference on Connected Health: Applications, 2016

2015
ASP-Based Encoding Model of Architecture Synthesis for Smart Cameras in Distributed Networks.
ACM Trans. Design Autom. Electr. Syst., 2015

Interface Based Memory Synthesis of Image Processing Applications in FPGA.
SIGARCH Comput. Archit. News, 2015

An embedded system for handwritten digit recognition.
J. Syst. Archit., 2015

Adaptive controller using runtime partial hardware reconfiguration for unmanned aerial vehicles (UAVs).
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Hardware isolation technique for IRC-based botnets detection.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A System on Reconfigurable Chip for Handwritten Digit Recognition.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
An ID and Address Protection Unit for NoC based Communication Architectures.
Proceedings of the 7th International Conference on Security of Information and Networks, 2014

Automatic UVM Environment Generation for Assertion-Based and Functional Verification of SystemC Designs.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

Self-Coordinated Target Assignment and Camera Handoff in Distributed Network of Embedded Smart Cameras.
Proceedings of the International Conference on Distributed Smart Cameras, 2014

A framework for rapid prototyping of embedded vision applications.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

2013
ACM HotMobile 2013 poster: RazorCam: a prototyping environment for video communication.
ACM SIGMOBILE Mob. Comput. Commun. Rev., 2013

Strategy for the Development of a Smart NDVI Camera System for Outdoor Plant Detection and Agricultural Embedded Systems.
Sensors, 2013

FPGA Implementation of Subcarrier Index Modulation OFDM Transceiver.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012
Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras.
Int. J. Reconfigurable Comput., 2012

Reducing communication costs on Dynamic Networks-on-Chip through runtime relocation of tasks.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

RAW Introduction.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Improving video communication in distributed smart camera systems through ROI-based video analysis and compression.
Proceedings of the Sixth International Conference on Distributed Smart Cameras, 2012

Hardware synthesis of recursive functions through partial stream rewriting.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Rapid prototyping of OpenCV image processing applications using ASP.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Integrated Temporal Planning, Module Selection and Placement of Tasks for Dynamic Networks-on-Chip.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Probabilistic framework for person tracking on embedded distributed smart cameras.
Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

Enabling communication infrastructure and protocol on embedded distributed smart cameras.
Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

2010
Heuristics for Flexible CMP Synthesis.
IEEE Trans. Computers, 2010

Scratch Detector - A FPGA Based System for Scratch Detection in Industrial Picture Development.
Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

Reconfigurable router for dynamic Networks-on-Chip.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

Performance Analysis of Hardware/Software Middleware in Network of Smart Camera Systems.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Application-driven architecture synthesis of on-chip Multiprocessor systems.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010

Hardware ORB Middleware for Distributed Smart Camera Systems.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Declarative Programming with Handel-C.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Reconfigurable Architecture for Distributed Smart Cameras.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Camera-based system for tracking and position estimation of humans.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

Auto-reconfiguration on self-organized intelligent platform.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs.
Microprocess. Microsystems, 2009

Automated architecture synthesis for parallel programs on FPGA multiprocessor systems.
Microprocess. Microsystems, 2009

Special issue on ReCoSoC 2007.
Microprocess. Microsystems, 2009

Answer Set versus Integer Linear Programming for Automatic Synthesis of Multiprocessor Systems from Real-Time Parallel Programs.
Int. J. Reconfigurable Comput., 2009

Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware.
Int. J. Reconfigurable Comput., 2009

Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs.
Proceedings of the Logic Programming and Nonmonotonic Reasoning, 2009

A new deadlock-free fault-tolerant routing algorithm for NoC interconnections.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Automatic Synthesis of Multiprocessor Systems from Parallel Programs under Preemptive Scheduling.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Makespan minimization in automatic synthesis of multiprocessor systems from parallel programs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

2007
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer.
J. VLSI Signal Process., 2007

Design of adaptive multiprocessor on chip systems.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A Dynamic Communication Structure for Dynamically Reconfigurable FPGAs.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Adaptive Network for Multiprocessing in Programmable Logic Devices.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Automatic Generation of Adaptive Multiprocessor Systems.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Embedded Vertex Shader in FPGA.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs.
Proceedings of the FPL 2007, 2007

SoPC architecture for a Key Point Detector.
Proceedings of the FPL 2007, 2007

Hardware/Software co-design of a key point detector on FPGA.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Introduction to reconfigurable computing - architectures, algorithms, and applications.
Springer, ISBN: 978-1-402-06088-5, 2007

2006
Dynamic reconfiguration of Distributed Arithmetic designs.
Int. J. Embed. Syst., 2006

A Dynamic Reconfigurable Hardware/Software Architecture for Object Tracking in Video Streams.
EURASIP J. Embed. Syst., 2006

Design and Implementation of an Object Tracker on a Reconfigurable System on Chip.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

A Flexible Reconfiguration Manager for the Erlangen Slot Machine.
Proceedings of the ARCS 2006, 2006

2005
CoreMap: a rapid prototyping environment for distributed reconfigurable systems.
Int. J. Embed. Syst., 2005

Online placement for dynamically reconfigurable devices.
Int. J. Embed. Syst., 2005

Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices.
IEEE Des. Test Comput., 2005

Defragmenting the Module Layout of a Partially Reconfigurable Device
CoRR, 2005

A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Building Up a Course in Reconfigurable Computing.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

A CMOS front-end architecture for hard-disk drive read-channel equalizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Packet Routing in Dynamically Changing Networks on Chip.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Experiences in Teaching Reconfigurable Computing at Erlangen University.
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005

Temporal Graph Placement on Mesh-Based Coarse Grain Reconfigurable Systems Using the Spectral Method.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Defragmenting the Module Layout of a Partially Reconfigurable Device.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004
Task scheduling for heterogeneous reconfigurable computers.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-Off Analysis.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

A New Approach for On-line Placement on Reconfigurable Devices.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

FPGA architecture extensions for preemptive multitasking and hardware defragmentation.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

A Dynamic NoC Approach for Communication in Reconfigurable Devices.
Proceedings of the Field Programmable Logic and Application, 2004

Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs.
Proceedings of the Field Programmable Logic and Application, 2004

Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices.
Proceedings of the Field Programmable Logic and Application, 2004

Generation of Distributed Arithmetic Designs for Reconfigurable Application.
Proceedings of the ARCS 2004, 2004

A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware.
Proceedings of the Organic and Pervasive Computing, 2004

2003
Synthesis of dataflow graphs for reconfigurable systems using temporal partitioning and temporal placement.
PhD thesis, 2003

A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

A new approach for reconfigurable massively parallel computers.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Temporal task clustering for online placement on reconfigurable hardware.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems.
Proceedings of the 2003 Design, 2003

2002
A Rapid Prototyping Environment for Distributed Reconfigurable Systems.
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

Temporal Partitioning and Sequencing of Dataflow Graphs on Reconfigurable Systems.
Proceedings of the Design and Analysis of Distributed Embedded Systems, IFIP 17<sup>th</sup> World Computer Congress, 2002

2001
Singular Value Decomposition on Distributed Reconfigurable Systems.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

2000
Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction.
Proceedings of the Field-Programmable Logic and Applications, 2000


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