Zhe Liu

According to our database, Zhe Liu authored at least 13 papers between 2017 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A 2.4dB NF +4.1dBm IIP3 Differential Dual-Feedforward-Based Noise-Cancelling LNTA With Complementary NMOS and PMOS Configuration.

Zhe Liu, Chirn Chye Boon, Yangtao Dong, Kaituo Yang

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A 0.092-mm² 2-12-GHz Noise-Cancelling Low-Noise Amplifier With Gain Improvement and Noise Reduction.

Zhe Liu, Chirn Chye Boon

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with +10dBm in-Band IIP3 in Current-Mode and 1.7dB NF in Voltage-Mode.

Kaituo Yang, Chirn Chye Boon, Zhe Liu, Jiaming Piao, Ting Guo, Yangtao Dong, Chenyang Li, Ao Zhou, Zhijie Yang, Xiaoying Wang, Yufeng Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 0.0078mm2 3.4mW Wideband Positive-feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting G_m Boosting.

Zhe Liu, Chirn Chye Boon, Chenyang Li, Kaituo Yang, Yangtao Dong, Ting Guo

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression.

Yangtao Dong, Chirn Chye Boon, Kaituo Yang, Zhe Liu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation.

Yangtao Dong, Chirn Chye Boon, Xin Ding, Chenyang Li, Zhe Liu

IEEE Trans. Very Large Scale Integr. Syst., 2021

A 1.75dB-NF 25mW 5GHz Transformer-Based Noise- Cancelling CMOS Receiver Front-End.

Kaituo Yang, Chirn Chye Boon, Guangyin Feng, Chenyang Li, Zhe Liu, Ting Guo, Xiang Yi, Yangtao Dong, Ao Zhou, Xiaoying Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020

Design of a Wideband Variable-Gain Amplifier With Self-Compensated Transistor for Accurate dB-Linear Characteristic in 65 nm CMOS Technology.

Lingshan Kong, Hang Liu, Xi Zhu, Chirn Chye Boon, Chenyang Li, Zhe Liu, Kiat Seng Yeo

IEEE Trans. Circuits Syst., 2020

Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line.

Qian Chen, Chirn Chye Boon, Xueyong Zhang, Chenyang Li, Yuan Liang, Zhe Liu, Ting Guo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018

A 253mW/channel 4TX/4RX pulsed chirping phased-array radar TRX in 65nm CMOS for X-band synthetic-aperture radar imaging.

Liheng Lou, Kai Tang, Bo Chen, Ting Guo, Yisheng Wang, Wensong Wang, Zhongyuan Fang, Zhe Liu, Yuanjin Zheng

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A DDS-Driven ADPLL Chirp Synthesizer with Ramp-Interpolating Linearization for FMCW Radar Application in 65nm CMOS.

Liheng Lou, Kai Tang, Zhongyuan Fang, Bo Chen, Ting Guo, Zhe Liu, Yuanjin Zheng

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A DLL-based Configurable Multi-Phase Clock Generator for True-Time-Delay Wideband FMCW Phased-Array in 40nm CMOS.

Zhe Liu, Liheng Lou, Zhongyuan Fang, Kai Tang, Ting Guo, Yuanjin Zheng

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

The Investigation and Optimisation of Phase-Induced Amplitude Attenuation in the Injection-Locked Ring Oscillators-Based Receiver.

Xiaopeng Yu, Zhe Liu, De Zhang Fan, Kiat Seng Yeo

Circuits Syst. Signal Process., 2017