Zhen Wang

Orcid: 0009-0003-8853-9915

Affiliations:
  • State Key Lab of Processors, Institute of Computing Technology, CAS, Beijing, China


According to our database1, Zhen Wang authored at least 9 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
DFU-E: A Dataflow Architecture for Edge DSP and AI Applications.
IEEE Trans. Parallel Distributed Syst., June, 2025

PANDA: Adaptive Prefetching and Decentralized Scheduling for Dataflow Architectures.
ACM Trans. Archit. Code Optim., June, 2025

Accelerating tensor multiplication by exploring hybrid product with hardware and software co-design.
J. Syst. Archit., 2025

Accelerating Authenticated Block Ciphers via RISC-V Custom Cryptography Instructions.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
Improving Utilization of Dataflow Unit for Multi-Batch Processing.
ACM Trans. Archit. Code Optim., March, 2024

2023
Accelerating Convolutional Neural Networks by Exploiting the Sparsity of Output Activation.
IEEE Trans. Parallel Distributed Syst., December, 2023

Alleviating Transfer Latency in DataFlow Accelerator for DSP Applications.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

ROMA: A Reconfigurable On-chip Memory Architecture for Multi-core Accelerators.
Proceedings of the IEEE International Conference on High Performance Computing & Communications, 2023

2022
A Loop Optimization Method for Dataflow Architecture.
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022


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