Yanhuan Liu

Orcid: 0009-0003-7151-6549

According to our database1, Yanhuan Liu authored at least 5 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2023
Accelerating Convolutional Neural Networks by Exploiting the Sparsity of Output Activation.
IEEE Trans. Parallel Distributed Syst., December, 2023

Alleviating Transfer Latency in DataFlow Accelerator for DSP Applications.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2021
RISC-NN: Use RISC, NOT CISC as Neural Network Hardware Infrastructure.
CoRR, 2021

Distilling Bit-level Sparsity Parallelism for General Purpose Deep Learning Acceleration.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2017
A high-performance FPGA-based LDPC decoder for solid-state drives.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017


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