Zheng Shi

Orcid: 0000-0003-4952-9389

Affiliations:
  • Zhejiang University, Institute of VLSI Design, Hangzhou, China


According to our database1, Zheng Shi authored at least 24 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
A BJT-Based CMOS Temperature Sensor With Duty-Cycle-Modulated Output and ±0.5°C (3σ) Inaccuracy From -40 °C to 125 °C.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 1-V Diode-Based Temperature Sensor with a Resolution FoM of 3.1pJ•K<sup>2</sup> in 55nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
A Dynamic-Biased Resistor-Based CMOS Temperature Sensor With a Duty-Cycle-Modulated Output.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 1770-µm<sup>2</sup> Leakage-Based Digital Temperature Sensor With Supply Sensitivity Suppression in 55-nm CMOS.
IEEE J. Solid State Circuits, 2020

2019
A Reliability-Oriented Startup Analysis of Injection-Locked Frequency Divider Based on Broken Symmetry Theory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Untrimmed BJT-Based Temperature Sensor With Dynamic Current-Gain Compensation in 55-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2018
A CMOS Temperature Sensor With Versatile Readout Scheme and High Accuracy for Multi-Sensor Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS.
Integr., 2018

Rate-Adaptive Protograph LDPC Codes for Multi-Level-Cell NAND Flash Memory.
IEEE Commun. Lett., 2018

2017
A novel layout automation flow to facilitate test chip design for standard cell characterization.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Design and automatic generation of area-efficient ring oscillator based addressable test chips.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015
Fast Level-Set-Based Inverse Lithography Algorithm for Process Robustness Improvement and Its Application.
J. Comput. Sci. Technol., 2015

A New On-chip Signal Generator for Charge-Based Capacitance Measurement Circuit.
J. Electron. Test., 2015

2014
SVM based layout retargeting for fast and regularized inverse lithography.
J. Zhejiang Univ. Sci. C, 2014

2013
Regularized level-set-based inverse lithography algorithm for IC mask synthesis.
J. Zhejiang Univ. Sci. C, 2013

A New Level-Set-Based Inverse Lithography Algorithm for Process Robustness Improvement with Attenuated Phase Shift Mask.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

2012
Array based HV/VH tree: an effective data structure for layout representation.
J. Zhejiang Univ. Sci. C, 2012

2011
Erratum to: A sparse matrix model-based optical proximity correction algorithm with model-based mapping between segments and control sites.
J. Zhejiang Univ. Sci. C, 2011

A sparse matrix model-based optical proximity correction algorithm with model-based mapping between segments and control sites.
J. Zhejiang Univ. Sci. C, 2011

Using NMOS transistors as switches for accuracy and area-efficiency in large-scale addressable test array.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A fully automated large-scale addressable test chip design with high reliability.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2007
An Automated and Fast OPC Algorithm for OPC-Aware Layout Design.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2005
Full-IC manufacturability check based on dense silicon imaging.
Sci. China Ser. F Inf. Sci., 2005

A new method for model based frugal OPC.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005


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