Xiaolang Yan

According to our database1, Xiaolang Yan authored at least 87 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Structured Dynamic Precision for Deep Neural Networks Quantization.
ACM Trans. Design Autom. Electr. Syst., January, 2023

Structured Term Pruning for Computational Efficient Neural Networks Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2022
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.
Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022

2021
Expected Energy Optimization for Real-Time Multiprocessor SoCs Running Periodic Tasks with Uncertain Execution Time.
IEEE Trans. Sustain. Comput., 2021

2020
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Xuantie-910: Innovating Cloud and Edge Computing by RISC-V.
Proceedings of the IEEE Hot Chips 32 Symposium, 2020

2019
A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

High Noise Tolerant R-Peak Detection Method Based on Deep Convolution Neural Network.
IEICE Trans. Inf. Syst., 2019

Fine-Grained Communication-Aware Task Scheduling Approach for Acyclic and Cyclic Applications on MPSoCs.
IEEE Access, 2019

2018
Curve fitting based shared cache partitioning scheme for energy saving.
IEICE Electron. Express, 2018

BFCO: A BPSO-Based Fine-Grained Communication Optimization Method for MPSoC.
IEEE Access, 2018

Energy-Efficient Fault-Tolerant Mapping and Scheduling on Heterogeneous Multiprocessor Real-Time Systems.
IEEE Access, 2018

2017
Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Providing Predictable Performance via a Slowdown Estimation Model.
ACM Trans. Archit. Code Optim., 2017

OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems.
ACM Trans. Archit. Code Optim., 2016

Light-weight one-cycle timing error correction based on hardware software co-design.
IEICE Electron. Express, 2016

EDSU: Error detection and sampling unified flip-flop with ultra-low overhead.
IEICE Electron. Express, 2016

2015
Functional Testbench Qualification by Mutation Analysis.
VLSI Design, 2015

Communication Optimizations for Multithreaded Code Generation from Simulink Models.
ACM Trans. Embed. Comput. Syst., 2015

Profiling and annotation combined method for multimedia application specific MPSoC performance estimation.
Frontiers Inf. Technol. Electron. Eng., 2015

Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model.
J. Electr. Comput. Eng., 2015

Fast Level-Set-Based Inverse Lithography Algorithm for Process Robustness Improvement and Its Application.
J. Comput. Sci. Technol., 2015

2014
SVM based layout retargeting for fast and regularized inverse lithography.
J. Zhejiang Univ. Sci. C, 2014

ILP Based Multithreaded Code Generation for Simulink Model.
IEICE Trans. Inf. Syst., 2014

Perceptual image quality assessment metric using mutual information of Gabor features.
Sci. China Inf. Sci., 2014

SoC processor for real-time object labeling in life camera streams with low line level latency.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Analysis and evaluation of per-flow delay bound for multiplexing models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Hierarchical Resampling Algorithm and Architecture for Distributed Particle Filters.
J. Signal Process. Syst., 2013

Performance Estimation Techniques With MPSoC Transaction-Accurate Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding.
J. Zhejiang Univ. Sci. C, 2013

Regularized level-set-based inverse lithography algorithm for IC mask synthesis.
J. Zhejiang Univ. Sci. C, 2013

Novel serpentine structure design method considering confidence level and estimation precision.
J. Zhejiang Univ. Sci. C, 2013

A Fast Self-Organizing Map Algorithm for Handwritten Digit Recognition.
Proceedings of the Multimedia and Ubiquitous Engineering, 2013

Particle state compression scheme for centralized memory-efficient particle filters.
Proceedings of the IEEE International Conference on Acoustics, 2013

A New Level-Set-Based Inverse Lithography Algorithm for Process Robustness Improvement with Attenuated Phase Shift Mask.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

2012
Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process.
J. Zhejiang Univ. Sci. C, 2012

Array based HV/VH tree: an effective data structure for layout representation.
J. Zhejiang Univ. Sci. C, 2012

A new via chain design method considering confidence level and estimation precision.
J. Zhejiang Univ. Sci. C, 2012

Code division multiple access/pulse position modulation ultra-wideband radio frequency identification for Internet of Things: concept and analysis.
Int. J. Commun. Syst., 2012

Design and Optimization of a CDMA-Based Multi-Reader Passive UHF RFID System for Dense Scenarios.
IEICE Trans. Commun., 2012

Weight sorting based scheme and architecture for distributed particle filters.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Hierarchical resampling architecture for distributed particle filters.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011
A robust motion estimation with center-biased diamond search and its parallel architecture for motion-compensated de-interlace.
J. Supercomput., 2011

A green-switch controller IC for cascade buck-boost converter with seamless transition over entire input and load range.
Microelectron. J., 2011

Efficient implementation of a cubic-convolution based image scaling engine.
J. Zhejiang Univ. Sci. C, 2011

Erratum to: A sparse matrix model-based optical proximity correction algorithm with model-based mapping between segments and control sites.
J. Zhejiang Univ. Sci. C, 2011

A sparse matrix model-based optical proximity correction algorithm with model-based mapping between segments and control sites.
J. Zhejiang Univ. Sci. C, 2011

Current oscillations and low-frequency noises in GaAs MESFET channels with sidegating bias.
J. Zhejiang Univ. Sci. C, 2011

A general communication performance evaluation model based on routing path decomposition.
J. Zhejiang Univ. Sci. C, 2011

An Efficient Compatibility-Based Test Data Compression and Its Decoder Architecture.
J. Electron. Test., 2011

Using NMOS transistors as switches for accuracy and area-efficiency in large-scale addressable test array.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Behavioral modeling of direct sampling mixer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A fully automated large-scale addressable test chip design with high reliability.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Discrete-time charge analysis for a digital RF charge sampling mixer.
J. Zhejiang Univ. Sci. C, 2010

A Low Delay Multiple Reader Passive RFID System Using Orthogonal TH-PPM IR-UWB.
Proceedings of the 19th International Conference on Computer Communications and Networks, 2010

COSMO: CO-Simulation with MATLAB and OMNeT++ for Indoor Wireless Networks.
Proceedings of the Global Communications Conference, 2010

A high efficient memory architecture for H.264/AVC motion compensation.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Simulink<sup>®</sup>-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation.
Integr., 2009

2008
A quasi fixed frequency constant on time controlled boost converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Analysis of Hybrid Translinear Circuit and Its Application.
Eng. Lett., 2007

A High Precision Bandgap Reference Used in Power Management ICs.
Eng. Lett., 2007

Phase noise analysis of oscillators with Sylvester representation for periodic time-varying modulus matrix by regular perturbations.
Sci. China Ser. F Inf. Sci., 2007

Explicit data organization SIMD instruction set architecture for media processors.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

An Automated and Fast OPC Algorithm for OPC-Aware Layout Design.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

An optimized linear skewing interleave scheme for on-chip multi-access memory systems.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.
Proceedings of the 44th Design Automation Conference, 2007

An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability.
Proceedings of the 16th Asian Test Symposium, 2007

An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
A Programmable Bitstream Parser for Multiple Video Coding Standards.
Proceedings of the First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August, 2006

Translinear Loop Principle and Identification of the Translinear Loops.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A BiCMOS Low Voltage Low Distortion Class AB Amplifier.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Load Share Controller IC and Its Control Strategy Design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Full-IC manufacturability check based on dense silicon imaging.
Sci. China Ser. F Inf. Sci., 2005

A high performance architecture of EBCOT encoder in JPEG 2000.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A simplified algorithm of JPEG2000 rate control for VLSI implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

Q-DPM: An Efficient Model-Free Dynamic Power Management Technique.
Proceedings of the 2005 Design, 2005

A new method for model based frugal OPC.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A novel data processing circuit in high-speed serial communication.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Tiling artifact reduction for JPEG2000 image at low bit-rate.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

Robust and Adaptive Dynamic Power Management for Time Varying System.
Proceedings of the Embedded Software and Systems, First International Conference, 2004

Joint Task Placement, Routing and Power Control for Low Power Mobile Grid Computing in Ad Hoc Network.
Proceedings of the Grid and Cooperative Computing, 2004

Heterogeneous Grid Computing for Energy Constrained Mobile Device.
Proceedings of the Embedded and Ubiquitous Computing, 2004

Power Consumption of Wireless NIC and Its Impact on Joint Routing and Power Control in Ad Hoc Network.
Proceedings of the Embedded and Ubiquitous Computing, 2004

2003
Equivalence Checking Using Independent Cuts.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003


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