Zhengyu Chen

Orcid: 0000-0001-5811-456X

Affiliations:
  • Northwestern University, Evanston, IL, USA


According to our database1, Zhengyu Chen authored at least 11 papers between 2016 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2021
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing.
IEEE J. Solid State Circuits, 2021

15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation.
IEEE J. Solid State Circuits, 2019

A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018

R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2016
Analysis and Design of Energy Efficient Time Domain Signal Processing.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016


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