Qiankai Cao
Orcid: 0000-0003-2812-3857
According to our database1,
Qiankai Cao authored at least 12 papers
between 2019 and 2026.
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Bibliography
2026
Proactive Power Management-Based Supply Regulation with Online Learning for Variation-Tolerant Workload-Aware Droop Mitigation in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
A 65-nm Humanoid Robot System-on-Chip Using Time-Domain 3-D Footstep Planning and Mixed-Signal ZMP Gait Scheduler With Inverse Kinematics.
IEEE J. Solid State Circuits, April, 2025
Modeling, Design and In-situ Demonstration of Bio-inspired Central Pattern Generator and Neuromorphic Computing Circuits for Complex Kinematic Control of Quadruped Robots.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
Humanoid Robot Control: A Mixed-Signal Footstep Planning SoC with ZMP Gait Scheduler and Neural Inverse Kinematics.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
A Mixed-signal 3D Footstep Planning SoC for Motion Control of Humanoid Robots with Embedded Zero-Moment-Point based Gait Scheduler and Neural Inverse Kinematics.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine Learning.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
2022
A Sparse Convolution Neural Network Accelerator for 3D/4D Point-Cloud Image Recognition on Low Power Mobile Device with Hopping-Index Rule Book for Efficient Coordinate Management.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier.
IEEE J. Solid State Circuits, 2021
2020
A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A Wearable Bio-signal Processing System with Ultra-low-power SoC and Collaborative Neural Network Classifier for Low Dimensional Data Communication.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
An Agent-Based Simulation Model for Operations in an Automatic Container Terminal with DTQC/AGV/ARMG.
Proceedings of the 11th International Conference on Computer Modeling and Simulation, 2019