Hai Zhou

IEEE Trans. Very Large Scale Integr. Syst., 2019

Vulnerability and Remedy of Stripped Function Logic Locking.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Resolving the Trilemma in Logic Encryption.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

BeSAT: Behavioral SAT-based Attack on Cyclic Logic Encryption.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

SigAttack: New High-level SAT-based Attack on Logic Encryptions.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

CycSAT-Unresolvable Cyclic Logic Encryption Using Unreachable States.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

CellScope: Automatically Specifying and Verifying Cellular Network Protocols.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGCOMM 2019 Conference Posters and Demos, 2019

An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing.

[BibT_eX]

[DOI]

Zhengyu Chen

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

Chapter Three - Multiobjectivism in Dark Silicon Age.

[BibT_eX]

[DOI]

Masoud Daneshtalab

Adv. Comput., 2018

R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing.

[BibT_eX]

[DOI]

Zhengyu Chen

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2017

An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

CycSAT: SAT-Based Attack on Cyclic Logic Encryptions.

[BibT_eX]

[DOI]

Ruifeng Jiang

IACR Cryptol. ePrint Arch., 2017

A Humble Theory and Application for Logic Encryption.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Double DIP: Re-Evaluating Security of Logic Encryption Algorithms.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

SAT-based Bit-flipping Attack on Logic Encryptions.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

A Comparative Investigation of Approximate Attacks on Logic Encryptions.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age.

[BibT_eX]

[DOI]

Proceedings of the 25th Euromicro International Conference on Parallel, 2017

Memristor-Based Clock Design and Optimization with In-Situ Tunability.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A Novel N-Retry Transactional Memory Model for Multi-Thread Programming.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Using Security Invariant To Verify Confidentiality in Hardware Design.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Network flow based cut redistribution and insertion for advanced 1D layout design.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

An efficient algorithm for stencil planning and optimization in E-beam lithography.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015

Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Multi-parameter clock skew scheduling.

[BibT_eX]

[DOI]

Integr., 2015

Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Synthesis of resilient circuits from guarded atomic actions.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Optimal and Efficient Algorithms for Multidomain Clock Skew Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

On error modeling and analysis of approximate adders.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Recovery-based resilient latency-insensitive systems.

[BibT_eX]

[DOI]

Xuan Zeng

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

SmipRef: An efficient method for multi-domain clock skew scheduling.

[BibT_eX]

[DOI]

Integr., 2013

An efficient method for gradient-aware dummy fill synthesis.

[BibT_eX]

[DOI]

Integr., 2013

Post-routing layer assignment for double patterning with timing critical paths consideration.

[BibT_eX]

[DOI]

Integr., 2013

Layout decomposition with pairwise coloring for multiple patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Structural transformation for best-possible obfuscation of sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Retiming for Soft Error Minimization Under Error-Latching Window Constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Resource-constrained high-level datapath optimization in ASIP design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Efficient design space exploration for component-based system design.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

An efficient algorithm for library-based cell-type selection in high-performance low-power designs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Clock skew scheduling for timing speculation.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Optimal prescribed-domain clock skew scheduling.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Buffer minimization in pipelined SDF scheduling on multi-core platforms.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Special Section on Multicore Parallel CAD: Algorithm Design and Programming.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

MSV-Driven Floorplanning.

[BibT_eX]

[DOI]

Qiang Ma

Zaichen Qian

Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Binning Optimization for Transparently-Latched Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

An efficient algorithm for multi-domain clock skew scheduling.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Integrated circuit white space redistribution for temperature optimization.

[BibT_eX]

[DOI]

Robert P. Dick

Proceedings of the Design, Automation and Test in Europe, 2011

Optimal multi-domain clock skew scheduling.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

A practical method for multi-domain clock skew optimization.

[BibT_eX]

[DOI]

Yanling Zhi

Xuan Zeng

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Parallel cross-layer optimization of high-level synthesis and physical design.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Post-routing layer assignment for double patterning.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Low power discrete voltage assignment under clock skew scheduling.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Multicore Parallelization of Min-Cost Flow for CAD Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering.

[BibT_eX]

[DOI]

Debasish Das

Kip Killpack

Chandramouli V. Kashyap

Abhijit Jas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Hybrid energy storage system integration for vehicles.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

iRetILP: an efficient incremental algorithm for min-period retiming under general delay model.

[BibT_eX]

[DOI]

Debasish Das

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

A Timing-Dependent Power Estimation Framework Considering Coupling.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

ACM Transactions on Design Automation of Electronic Systems (TODAES) special section call for papers: Parallel CAD: Algorithm design and programming.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Gate Sizing by Lagrangian Relaxation Revisited.

[BibT_eX]

[DOI]

Debasish Das

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An efficient current-based logic cell model for crosstalk delay analysis.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Binning optimization based on SSTA for transparently-latched circuits.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Retiming and resynthesis with sweep are complete for sequential transformation.

[BibT_eX]

[DOI]

Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Exception triggered DoS attacks on wireless networks.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

Multicore parallel min-cost flow algorithm for CAD applications.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Statistical reliability analysis under process variation and aging effects.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Provably good and practically efficient algorithms for CMP dummy fill.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Risk aversion min-period retiming under process variations.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Exploring adjacency in floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis.

[BibT_eX]

[DOI]

Nikolaos D. Liveris

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Rectilinear Steiner Tree.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Rectilinear Spanning Tree.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Circuit Retiming: An Incremental Approach.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Circuit Retiming.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Fast Estimation of Timing Yield Bounds for Process Variations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

A new efficient retiming algorithm derived by formal manipulation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Optimizing wirelength and routability by searching alternative packings in floorplanning.

[BibT_eX]

[DOI]

Chiu-Wing Sham

Evangeline F. Y. Young

ACM Trans. Design Autom. Electr. Syst., 2008

EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm.

[BibT_eX]

[DOI]

Jieyi Long

Seda Ogrenci Memik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction.

[BibT_eX]

[DOI]

Jieyi Long

Seda Ogrenci Memik

Proceedings of the 2008 International Symposium on Physical Design, 2008

Linear constraint graph for floorplan optimization with soft blocks.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

State space abstraction for parameterized self-stabilizing embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 8th ACM & IEEE International conference on Embedded software, 2008

An efficient incremental algorithm for min-area retiming.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications.

[BibT_eX]

[DOI]

Nikolaos D. Liveris

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Advances in Computation of the Maximum of a Set of Gaussian Random Variables.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Unified Incremental Physical-Level and High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.

[BibT_eX]

[DOI]

Jianfeng Luo

Subramanian Rajagopalan

Shabbir H. Batterywala

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Timing budgeting under arbitrary process variations.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Address generation for nanowire decoders.

[BibT_eX]

[DOI]

Ming-Yang Kao

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Design closure driven delay relaxation based on convex cost network flow.

[BibT_eX]

[DOI]

Aiguo Xie

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Fast Min-Cost Buffer Insertion under Process Variations.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Retiming for Synchronous Data Flow Graphs.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

New Block-Based Statistical Timing Analysis Approaches Without Moment Matching.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Buffer Insertion for Yield Optimization Under Process Variations.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Statistical Timing Yield Optimization by Gate Sizing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Clustering for Processing Rate Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Statistical Timing Analysis With Coupling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Gate-size optimization under timing constraints for coupling-noise reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Optimal wire retiming without binary search.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An Efficient Data Structure for Maxplus Merge in Dynamic Programming.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Statistical timing verification for transparently latched circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Yield-Aware Cache Architectures.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Processing Rate Optimization by Sequential System Floorplanning.

[BibT_eX]

[DOI]

Ping-Chih Wu

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Advances in Computation of the Maximum of a Set of Random Variables.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A revisit to floorplan optimization by Lagrangian relaxation.

[BibT_eX]

[DOI]

Chris C. N. Chu

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Optimal jumper insertion for antenna avoidance under ratio upper-bound.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

An efficient retiming algorithm under setup and hold constraints.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Wire retiming as fixpoint computation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Spanning graph-based nonrectilinear steiner tree algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Timing yield estimation using statistical static timing analysis.

[BibT_eX]

[DOI]

Min Pan

Chris C. N. Chu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A unified framework for statistical timing analysis with coupling and multiple input switching.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Statistical gate sizing for timing yield optimization.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Trade-off between latch and flop for min-period sequential circuit designs with crosstalk.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Efficient algorithms for buffer insertion in general circuits based on network flow.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Leakage power optimization with dual-Vth library in high-level synthesis.

[BibT_eX]

[DOI]

Xiaoyong Tang

Proceedings of the 42nd Design Automation Conference, 2005

Incremental exploration of the combined physical and behavioral design space.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications.

[BibT_eX]

[DOI]

Nikolaos D. Liveris

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Deriving a new efficient algorithm for min-period retiming.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Interconnect estimation without packing via ACG floorplans.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Yield driven gate sizing for coupling-noise reduction under uncertainty.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Retiming for wire pipelining in system-on-chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Efficient Steiner tree construction based on spanning graphs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Optimal gate sizing for coupling-noise reduction.

[BibT_eX]

[DOI]

Chris C. N. Chu

Proceedings of the 2004 International Symposium on Physical Design, 2004

ACG-Adjacent Constraint Graph for General Floorplans.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A Flexible Data Structure for Efficient Buffer Insertion.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Clock schedule verification under process variations.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Timing macro-modeling of IP blocks with crosstalk.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Minimal period retiming under process variations.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Wire Retiming for System-on-Chip by Fixpoint Computation.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Efficient octilinear Steiner tree construction based on spanning graphs.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Timing analysis with crosstalk is a fixpoint on a complete lattice.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

BDD Based Procedures for a Theory of Equality with Uninterpreted Functions.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2003

Timing Verification with Crosstalk for Transparently Latched Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Interconnect-driven floorplanning by searching alternative packings.

[BibT_eX]

[DOI]

Chiu-Wing Sham

Evangeline F. Y. Young

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Efficient minimum spanning tree construction without Delaunay triangulation.

[BibT_eX]

[DOI]

William Nicholls

Inf. Process. Lett., 2002

Clock schedule verification with crosstalk.

[BibT_eX]

[DOI]

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Track assignment: a desirable intermediate step between global routing and detailed routing.

[BibT_eX]

[DOI]

Shabbir H. Batterywala

William Nicholls

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001

Buffer minimization in pass transistor logic.

[BibT_eX]

[DOI]

Adnan Aziz

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Timing Analysis with Crosstalk as Fixpoints on Complete Lattice.

[BibT_eX]

[DOI]

William Nicholls

Proceedings of the 38th Design Automation Conference, 2001

2000

Simultaneous routing and buffer insertion with restrictions onbuffer locations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Optimal low power X OR gate decomposition.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

Global routing with crosstalk constraints.

[BibT_eX]

[DOI]

Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

Integrated floorplanning and interconnect planning.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

Optimal river routing with crosstalk constraints.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1998

1997

Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

An exact gate decomposition algorithm for low-power technology mapping.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

An optimal algorithm for river routing with crosstalk constraints.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Optimal non-uniform wire-sizing under the Elmore delay model.

[BibT_eX]

[DOI]

Chung-Ping Chen