Zhenxin Zhao

Orcid: 0000-0003-4902-353X

According to our database1, Zhenxin Zhao authored at least 18 papers between 2018 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
VLM-CAD: VLM-Optimized Collaborative Agent Design Workflow for Analog Circuit Sizing.
CoRR, January, 2026

ChipMate: Design-experience-driven chip recommendation framework based on multi-agent collaboration.
Microelectron. J., 2026

Utilizing large language models for automated extraction of radio-frequency circuit metrics from scientific publications.
Microelectron. J., 2026

Reliable design of millimeter-wave filters: A physically-verified adaptive surrogate optimization approach.
Microelectron. J., 2026

2025
Automated Topology Synthesis of Analog Integrated Circuits With Frequency Compensation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

2024
Acceleration for Efficient Automated Generation of Operational Amplifiers.
Sensors, June, 2024

2023
Signal-Division-Aware Analog Circuit Topology Synthesis Aided by Transfer Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

2022
Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Reinforcement-Learning-based Mixed-Signal IC Placement for Fogging Effect Control.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Fogging-Effect-Aware Mixed-Signal IC Placement with Reinforcement Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Deep Reinforcement Learning for Analog Circuit Structure Synthesis.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2020
An Automated Topology Synthesis Framework for Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Deep Reinforcement Learning for Analog Circuit Sizing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Advanced Transitive-Closure-Graph-Based Placement Representation for Analog Layout Design.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Placement with Sequence-Pair-Driven TCG for Advanced Analog Constraints.
Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2020

2019
Graph-Grammar-Based Analog Circuit Topology Synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Fast Performance Evaluation for Analog Circuit Synthesis Frameworks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018


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