Zhenyu Liu

Orcid: 0000-0002-8816-766X

Affiliations:
  • Tsinghua University, TNList, Beijing, China
  • Waseda University, Kitakyushu, Japan (2004 - 2009)
  • Beijing Institute of Technology, China (PhD 2002)


According to our database1, Zhenyu Liu authored at least 88 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Optimize x265 Rate Control: An Exploration of Lookahead in Frame Bit Allocation and Slice Type Decision.
IEEE Trans. Image Process., 2019

A Block-Floating-Point Arithmetic Based FPGA Accelerator for Convolutional Neural Networks.
Proceedings of the 2019 IEEE Global Conference on Signal and Information Processing, 2019

2018
Parallel Content-Aware Adaptive Quantization-Oriented Lossy Frame Memory Recompression for HEVC.
IEEE Trans. Circuits Syst. Video Technol., 2018

CNN Based CU Partition Mode Decision Algorithm for HEVC Inter Coding.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

Rate Control Optimization of X265 Using Information from Quarter-Resolution Pre-Motion-Estimation.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

Enhance the HEVC Fast Intra CU Mode Decision Based on Convolutional Neural Network by Corner Power Estimation.
Proceedings of the 2018 Data Compression Conference, 2018

Computation Error Analysis of Block Floating Point Arithmetic Oriented Convolution Neural Network Accelerator Design.
Proceedings of the Thirty-Second AAAI Conference on Artificial Intelligence, 2018

2017
Computation Error Analysis of Block Floating Point Arithmetic Oriented Convolution Neural Network Accelerator Design.
CoRR, 2017

Data-centric computation mode for convolution in deep neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Coding sensitive based approximation algorithm for power efficient VBS-DCT VLSI design in HEVC hardwired Intra encoder.
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017

CNN oriented fast PU mode decision for HEVC hardwired intra encoder.
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017

Sensitivity-based acceleration and compression algorithm for convolution neural network.
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017

A 200MHZ 202.4GFLOPS@10.8W VGG16 accelerator in Xilinx VX690T.
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017

2016
A High-Throughput and Multi-Parallel VLSI Architecture for HEVC Deblocking Filter.
IEEE Trans. Multim., 2016

CU Partition Mode Decision for HEVC Hardwired Intra Encoder Using Convolution Neural Network.
IEEE Trans. Image Process., 2016

Lossless Frame Memory Compression Using Pixel-Grain Prediction and Dynamic Order Entropy Coding.
IEEE Trans. Circuits Syst. Video Technol., 2016

Hardware Oriented Enhanced Category Determination Based on CTU Boundary Deblocking Strength Prediction for SAO in HEVC Encoder.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

HEVC fast FME algorithm using IME RD-costs based error surface fitting scheme.
Proceedings of the 2016 Visual Communications and Image Processing, 2016

Error models of finite word length arithmetic in CNN accelerator design.
Proceedings of the 2016 Visual Communications and Image Processing, 2016

CNN oriented fast HEVC intra CU mode decision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Multi-feature based fast depth decision in HEVC inter prediction for VLSI implementation.
Proceedings of the 9th International Congress on Image and Signal Processing, 2016

A low power lossy frame memory recompression algorithm.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2016

2015
Cluster Cache Monitor: Leveraging the Proximity Data in CMP.
Int. J. Parallel Program., 2015

An efficient interpolation filter VLSI architecture for HEVC standard.
EURASIP J. Adv. Signal Process., 2015

Deblocking strength prediction based CTU-level SAO category determination in HEVC encoder.
Proceedings of the 2015 Visual Communications and Image Processing, 2015

VLSI friendly fast CU/PU mode decision for HEVC intra encoding: Leveraging convolution neural network.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

Pixel-grain prediction and K-order UEG-rice entropy coding oriented lossless frame memory compression for motion estimation in HEVC.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

2014
A Mode Mapping and Optimized MV Conjunction Based H.264/SVC to H.264/AVC Transcoder with Medium-Grain Quality Scalability for Videoconferencing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Fast Mode and Depth Decision for HEVC Intra Prediction Based on Edge Detection and Partition Reconfiguration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Binary classification based linear rate estimation model for HEVC RDO.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Linear adaptive search range model for uni-prediction and motion analysis for bi-prediction in HEVC.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Low complexity SAO in HEVC base on class combination, pre-decision and merge separation.
Proceedings of the 19th International Conference on Digital Signal Processing, 2014

Linear Rate Estimation Model for HEVC RDO Using Binary Classification Based Regression.
Proceedings of the Data Compression Conference, 2014

HDTV1080p HEVC Intra encoder with source texture based CU/PU mode pre-decision.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Hardware oriented category pre-determination algorithm for SAO in HEVC.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2014

2013
Improving Cache Partitioning Algorithms for Pseudo-LRU Policies.
IEICE Trans. Inf. Syst., 2013

Low-Complexity Hybrid-Domain H.264/SVC to H.264/AVC Spatial Transcoding with Drift Compensation for Videoconferencing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A Drift-Constrained Frequency-Domain Ultra-Low-Delay H.264/SVC to H.264/AVC Transcoder with Medium-Grain Quality Scalability for Videoconferencing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Bayesian Theory Based Adaptive Proximity Data Accessing for CMP Caches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Content-Aware Write Reduction Mechanism of 3D Stacked Phase-Change RAM Based Frame Store in H.264 Video Codec System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Cluster Cache Monitor.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

A Low-Complexity Quantization-Domain H.264/SVC to H.264/AVC Transcoder with Medium-Grain Quality Scalability.
Proceedings of the Advances in Multimedia Modeling, 19th International Conference, 2013

Fast mode and depth decision HEVC intra prediction based on edge detection and partitioning reconfiguration.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013

Security Memory System for Mobile Device or Computer Against Memory Attacks.
Proceedings of the Trustworthy Computing and Services, 2013

Fully pipelined DCT/IDCT/Hadamard unified transform architecture for HEVC Codec.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A mode-mapping and optimized MV conjunction based MGS-scalable SVC to AVC IPPP transcoder.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Content-aware write reduction mechanism of phase-change RAM based Frame Store in H.264 Video codec system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Fast HEVC intra mode decision using matching edge detector and kernel density estimation alike histogram generation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Fast prediction mode decision with hadamard transform based rate-distortion cost estimation for HEVC intra coding.
Proceedings of the IEEE International Conference on Image Processing, 2013

Bayesian theory oriented Optimal Data-Provider Selection for CMP.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

41.7BN-pixels/s reconfigurable intra prediction architecture for HEVC 2560×1600 encoder.
Proceedings of the IEEE International Conference on Acoustics, 2013

Fast intra prediction for HEVC based on pixel gradient statistics and mode refinement.
Proceedings of the 2013 IEEE China Summit and International Conference on Signal and Information Processing, 2013

2012
A Videoconferencing-Oriented Hybrid-Domain H.264/SVC to H.264/AVC Spatial Transcoder.
Proceedings of the Advances in Multimedia Information Processing - PCM 2012, 2012

Wear-Resistant Hybrid Cache Architecture with Phase Change Memory.
Proceedings of the Seventh IEEE International Conference on Networking, 2012

A pixel-domain mode-mapping based SVC-to-AVC transcoder with coarse grain quality scalability.
Proceedings of the 21st International Conference on Pattern Recognition, 2012

Lagrangian multiplier optimization using correlations in residues.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

Lagrangian Multiplier Optimization Using Markov Chain Based Rate and Piecewise Approximated Distortion Models.
Proceedings of the 2012 Data Compression Conference, Snowbird, UT, USA, April 10-12, 2012, 2012

2011
Register Length Analysis and VLSI Optimization of VBS Hadamard Transform in H.264/AVC.
IEEE Trans. Circuits Syst. Video Technol., 2011

A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction.
IEICE Trans. Electron., 2011

One-round renormalization based 2-bin/cycle H.264/AVC CABAC encoder.
Proceedings of the 18th IEEE International Conference on Image Processing, 2011

2010
Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2009
Motion Estimation Optimization for H.264/AVC Using Source Image Edge Features.
IEEE Trans. Circuits Syst. Video Technol., 2009

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis.
IEEE J. Solid State Circuits, 2009

Hardware optimizations of variable block size Hadamard transform for H.264/AVC FRExt.
Proceedings of the International Conference on Image Processing, 2009

2008
Motion Feature and Hadamard Coefficient-Based Fast Multiple Reference Frame Motion Estimation for H.264.
IEEE Trans. Circuits Syst. Video Technol., 2008

Content-Aware Fast Motion Estimation for H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Hardware-oriented direction-based fast fractional motion estimation algorithm in H.264/AVC.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Fast motion estimation for H.264/AVC using image edge features.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations.
IEICE Trans. Inf. Syst., 2007

Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

H.264/AVC Fractional Motion Estimation Engine with Computation Reusing in HDTV1080P Real-Time Encoding Applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

32-Parallel SAD Tree Hardwired Engine for Variable Block Size Motion Estimation in HDTV1080P Real-Time Encoding Application.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Enhanced Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Ultra Low-Complexity Fast Variable Block Size Motion Estimation Algorithm in H.264/AVC.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

VLSI Oriented Fast Multiple Reference Frame Motion Estimation Algorithm for H.264/AVC.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

VLSI friendly edge gradient detection based multiple reference frames motion estimation optimization for H.264/AVC.
Proceedings of the 15th European Signal Processing Conference, 2007

2006
A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC.
IEICE Trans. Electron., 2006

System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Low-Pass Filter Based Vlsi Oriented Variable Block Size Motion Estimation Algorithm for H.264.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Enhanced Partial Distortion Sorting Fast Motion Estimation Algorithm for Low-Power Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005


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