Yiqing Huang
Affiliations:- Waseda University, Kitakyushu, Japan
According to our database1,
Yiqing Huang
authored at least 33 papers
between 2007 and 2012.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2012
Low-Complexity Coarse-Level Mode-Mapping Based H.264/AVC to H.264/SVC Spatial Transcoding for Video Conferencing.
IEICE Trans. Inf. Syst., 2012
2011
Content Based Coarse to Fine Adaptive Interpolation Filter for High Resolution Video Coding.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Fast H.264/AVC DIRECT Mode Decision Based on Mode Selection and Predicted Rate-Distortion Cost.
IEICE Trans. Inf. Syst., 2011
Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4k×4k@60 fps.
IEICE Trans. Electron., 2011
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011
Adaptive fast DIRECT mode decision algorithm using mode and Lagrangian cost prediction for B frame in H.264/AVC.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011
2010
Constant Bit-Rate Multi-Stage Rate Control for Rate-Distortion Optimized H.264/AVC Encoders.
IEICE Trans. Inf. Syst., 2010
Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k×4k@60 fps.
IEICE Trans. Electron., 2010
Fully Utilized and Low Design Effort Architecture for H.264/AVC Intra Predictor Generation.
Proceedings of the Advances in Multimedia Modeling, 2010
2009
Macroblock Feature Based Adaptive Propagate Partial SAD Architecture for HDTV Application.
IPSJ Trans. Syst. LSI Des. Methodol., 2009
Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
VLSI Oriented Fast Motion Estimation Algorithm Based on Pixel Difference, Block Overlapping and Motion Feature Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
A Hardware Accelerator with Variable Pixel Representation & Skip Mode Prediction for Feature Point Detection Part of SIFT Algorithm.
Proceedings of the IAPR Conference on Machine Vision Applications (IAPR MVA 2009), 2009
On bit allocation and Lagrange Multiplier adjustment for rate-distortion optimized H.264 rate control.
Proceedings of the 2009 IEEE International Workshop on Multimedia Signal Processing, 2009
Proceedings of the 2009 IEEE International Workshop on Multimedia Signal Processing, 2009
Content aware configurable architecture for H.264/AVC integer motion estimation engine.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
Macroblock feature and motion involved multi-stage fast inter mode decision algorithm in H.264/AVC video coding.
Proceedings of the International Conference on Image Processing, 2009
Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder.
Proceedings of the 16th International Conference on Digital Signal Processing, 2009
A Macroblock-Level Rate Control Algorithm for H.264/AVC Video Coding with Context-Adaptive MAD Prediction Model.
Proceedings of the International Conference on Computer Modeling and Simulation, 2009
Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Rate-distortion optimized multi-stage rate control algorithm for H.264/AVC video coding.
Proceedings of the 17th European Signal Processing Conference, 2009
Fast inter mode decision algorithm based on macroblock and motion feature analysis for H.264/AVC video coding.
Proceedings of the 17th European Signal Processing Conference, 2009
2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Proceedings of the International Workshop on Multimedia Signal Processing, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 2008 16th European Signal Processing Conference, 2008
Compressor tree based processing element optimization in propagate partial SAD architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
VLSI friendly edge gradient detection based multiple reference frames motion estimation optimization for H.264/AVC.
Proceedings of the 15th European Signal Processing Conference, 2007