Zhenzhi Wu

Orcid: 0000-0002-7859-7818

According to our database1, Zhenzhi Wu authored at least 22 papers between 2014 and 2022.

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Bibliography

2022
LIAF-Net: Leaky Integrate and Analog Fire Network for Lightweight and Efficient Spatiotemporal Information Processing.
IEEE Trans. Neural Networks Learn. Syst., 2022

Modeling learnable electrical synapse for high precision spatio-temporal recognition.
Neural Networks, 2022

Convolution of Convolution: Let Kernels Spatially Collaborate.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

2021
Learnable Heterogeneous Convolution: Learning both topology and strength.
Neural Networks, 2021

Hybrid neural state machine for neural network.
Sci. China Inf. Sci., 2021

2020
Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation.
IEEE J. Solid State Circuits, 2020

Accurate and Efficient LIF-Nets for 3D Detection and Recognition.
IEEE Access, 2020

ARLIF: A Flexible and Efficient Recurrent Neuronal Model for Sequential Tasks.
Proceedings of the Human Brain and Artificial Intelligence - Second International Workshop, 2020

2019
Safe-Net: Solid and Abstract Feature Extraction Network for Pedestrian Attribute Recognition.
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

2018
GXNOR-Net: Training deep neural networks with ternary weights and activations without full-precision memory under a unified discretization framework.
Neural Networks, 2018

2017
Computational Complexity Analysis of FEC Decoding on SDR Platforms.
J. Signal Process. Syst., 2017

Gated XNOR Networks: Deep Neural Networks with Ternary Weights and Activations under a Unified Discretization Framework.
CoRR, 2017

2016
High-Accuracy Compressed Sensing Decoder Based on Adaptive (ℓ<sub>0</sub>, ℓ<sub>1</sub>) Complex Approximate Message Passing: Cross-layer Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015
High-Throughput Trellis Processor for Multistandard FEC Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Loop acceleration and instruction repeat support for application specific instruction-set processors.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A contention-free memory subsystem for 5G Turbo decoder with flexible degree of parallelism.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Benefit and cost of cross sliding window scheduling for low latency 5G Turbo decoding.
Proceedings of the 2015 IEEE/CIC International Conference on Communications in China, 2015

2014
A conflict-free access method for parallel turbo decoder.
Proceedings of the Sixth International Conference on Wireless Communications and Signal Processing, 2014

Memory sharing techniques for multi-standard high-throughput FEC decoder.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Matrix reordering techniques for memory conflict reduction for pipelined QC-LDPC decoder.
Proceedings of the 2014 IEEE/CIC International Conference on Communications in China, 2014

FPGA implementation of a multi-algorithm parallel FEC for SDR platforms.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Flexible multistandard FEC processor design with ASIP methodology.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014


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