Shuangchen Li
Orcid: 0000-0002-0021-6907
According to our database1,
Shuangchen Li
authored at least 72 papers
between 2011 and 2023.
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Bibliography
2023
E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption.
IEEE Micro, 2023
Multi-target reconstruction of fluorescence molecular tomography based on blind source separation.
Proceedings of the Medical Imaging 2023: Image Processing, 2023
Based on model-driven fast iterative shrinkage thresholding network for bioluminescence tomography reconstruction.
Proceedings of the Medical Imaging 2023: Image Processing, 2023
DF-GAS: a Distributed FPGA-as-a-Service Architecture towards Billion-Scale Graph-based Approximate Nearest Neighbor Search.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Structure-fused deep 3D hierarchical network: A bioluminescence tomography scheme for different imaging objects.
Proceedings of the 45th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2023
2022
Efficient Processing of Sparse Tensor Decomposition via Unified Abstraction and PE-Interactive Architecture.
IEEE Trans. Computers, 2022
Neurocomputing, 2022
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network.
IEEE Access, 2022
184QPS/W 64Mb/mm<sup>2</sup>3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
2021
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Proceedings of the 15th USENIX Symposium on Operating Systems Design and Implementation, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
End-To-End Bioluminescence Tomography Reconstruction Based On Convolution Neural Network Scheme.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
2020
ACM Trans. Archit. Code Optim., 2020
Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation.
IEEE J. Solid State Circuits, 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the 37th International Conference on Machine Learning, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020
2019
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.
IEEE Trans. Parallel Distributed Syst., 2019
Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints.
CoRR, 2019
NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs.
IEEE Comput. Archit. Lett., 2019
Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
PhD thesis, 2018
Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Comput. Archit. Lett., 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the International Symposium on Memory Systems, 2018
AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018
2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications.
ACM Trans. Design Autom. Electr. Syst., 2016
Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power.
IEEE Micro, 2016
NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Micro, 2015
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
2013
Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications.
Proceedings of the Design, Automation and Test in Europe, 2013
Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression.
IEICE Trans. Electron., 2011