Shuangchen Li

According to our database¹, Shuangchen Li authored at least 56 papers between 2011 and 2020.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Book

In proceedings

Article

PhD thesis

Other

Links

On csauthors.net:

Bibliography

2020

NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2020

Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

GNNAdvisor: An Efficient Runtime System for GNN Acceleration on GPUs.

[BibT_eX]

[DOI]

CoRR, 2020

DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Boosting Deep Neural Network Efficiency with Dual-Module Inference.

[BibT_eX]

[DOI]

Proceedings of the 37th International Conference on Machine Learning, 2020

NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators.

[BibT_eX]

[DOI]

Marzieh Lenjani

Patricia Gonzalez-Guerrero

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2019

Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints.

[BibT_eX]

[DOI]

CoRR, 2019

NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2019

Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Memory Trojan Attack on Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Memory-Bound Proof-of-Work Acceleration for Blockchain Applications.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Memory-Centric Architectures: Bridging the Gap Between Compute and Memory.

[BibT_eX]

[DOI]

Shuangchen Li

PhD thesis, 2018

Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

In-memory multiplication engine with SOT-MRAM based stochastic computing.

[BibT_eX]

[DOI]

CoRR, 2018

Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

GraphIA: an in-situ accelerator for large-scale graph processing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2018

AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

RADAR: a 3D-reRAM based DNA alignment accelerator architecture.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017

DRISA: a DRAM-based reconfigurable in-situ accelerator.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Building energy-efficient multi-level cell STT-RAM caches with data compression.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power.

[BibT_eX]

[DOI]

John (Jack) Morgan Sampson

Vijaykrishnan Narayanan

IEEE Micro, 2016

NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Architecture design with STT-RAM: Opportunities and challenges.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications.

[BibT_eX]

[DOI]

John (Jack) Morgan Sampson

Yuan Xie

Vijaykrishnan Narayanan

IEEE Micro, 2015

Leveraging nonvolatility for architecture design with emerging NVM.

[BibT_eX]

[DOI]

Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Architecture exploration for ambient energy harvesting nonvolatile processors.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Ambient energy harvesting nonvolatile processors: from circuit to system.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Nonvolatile memory allocation and hierarchy optimization for high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops.

[BibT_eX]

[DOI]

Proceedings of the 38th European Solid-State Circuit conference, 2012

A compression-based area-efficient recovery architecture for nonvolatile processors.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A hierarchical C2RTL framework for FIFO-connected stream applications.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2011

Shuangchen Li

Timeline

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On csauthors.net:

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