Zhicong Xie

According to our database, Zhicong Xie authored at least 7 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM.

Shouyi Yin, Tianyi Lu, Zhicong Xie, Leibo Liu, Shaojun Wei

IEEE Trans. Very Large Scale Integr. Syst., 2018

Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays.

Shouyi Yin, Zhicong Xie, Chenyue Meng, Peng Ouyang, Leibo Liu, Shaojun Wei

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis.

Shouyi Yin, Tianyi Lu, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei

IEEE Access, 2018

2017

Memory fartitioning-based modulo scheduling for high-level synthesis.

Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only).

Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM.

Shouyi Yin, Zhicong Xie, Shaojun Wei

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Multibank memory optimization for parallel data access in multiple data arrays.

Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei

Proceedings of the 35th International Conference on Computer-Aided Design, 2016