Zhijie Zhan

According to our database¹, Zhijie Zhan authored at least 2 papers between 2024 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

A 28-nm 0.8M-Weights/mm<sup>2</sup> 9.1-TOPS/mm<sup>2</sup> All-Analog SRAM-Based Compute-in-Memory Macro Using Fine-Grained Structured Pruning With Adaptive-Ranging ADC.

[BibT_eX]

[DOI]

Tsung-Yung Jonathan Chang

Atsutake Kosuge

Mototsugu Hamada

Tadahiro Kuroda

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026

2024

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2024

Zhijie Zhan

Timeline

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Bibliography

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