Tadahiro Kuroda
Orcid: 0000-0003-0617-1057
According to our database1,
Tadahiro Kuroda
authored at least 228 papers
between 1994 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2006, "For contributions to low-power and high-speed very large scale integrated (VLSI) design.".
Timeline
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Bibliography
2024
IPSJ Trans. Syst. LSI Des. Methodol., 2024
2023
Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface.
IEICE Trans. Electron., July, 2023
A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum.
IEEE Micro, 2023
A 7-nm FinFET 1.2-TB/s/mm<sup>2</sup> 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver.
IEEE J. Solid State Circuits, 2023
A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique.
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023
A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications.
IEEE Trans. Instrum. Meas., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network.
IEEE Open J. Circuits Syst., 2022
A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC.
IEEE J. Solid State Circuits, 2022
A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique.
Proceedings of the IEEE Sensors Applications Symposium, 2022
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A 7-nm FinFET 1.2-TB/s/mm<sup>2</sup> 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A 5-GHz 0.15-mm<sup>2</sup> Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.
IEEE J. Solid State Circuits, 2019
IEICE Trans. Electron., 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.
IEEE J. Solid State Circuits, 2018
Int. J. Netw. Comput., 2018
Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers.
IEICE Trans. Electron., 2018
Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Balanced Mini-Batch Training for Imbalanced Image Data Classification with Neural Network.
Proceedings of the First International Conference on Artificial Intelligence for Industries, 2018
2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver.
IEEE J. Solid State Circuits, 2016
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories.
IEEE J. Solid State Circuits, 2016
Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO.
IEICE Trans. Electron., 2016
Proceedings of the 2016 International Conference on Wireless Networks and Mobile Communications, 2016
Proceedings of the International SoC Design Conference, 2016
Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Transponder Array System with Universal On-Sheet Reference Scheme for Wireless Mobile Sensor Networks without Battery or Oscillator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
IEICE Trans. Electron., 2015
IEICE Trans. Electron., 2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory.
Proceedings of the Symposium on VLSI Circuits, 2015
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer.
Proceedings of the Symposium on VLSI Circuits, 2015
10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Computers, 2014
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
Wearable sensor-based human activity recognition from environmental background sounds.
J. Ambient Intell. Humaniz. Comput., 2014
Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage.
IEICE Trans. Electron., 2014
A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Micro, 2013
IEEE J. Solid State Circuits, 2013
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS.
IEEE J. Solid State Circuits, 2013
IEICE Trans. Inf. Syst., 2013
Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS.
IEICE Trans. Electron., 2013
A 0.8V 1.1pJ/bit inductive-coupling receiver with pulse extracting clock recovery circuit and intermittently operating LNA.
Proceedings of the 2013 IEEE Radio and Wireless Symposium, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Retrodirective transponder array with universal on-sheet reference for wireless mobile sensor networks without battery or oscillator.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE International Conference on Image Processing, 2013
Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2012
1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller.
IEEE J. Solid State Circuits, 2012
A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS.
IEEE J. Solid State Circuits, 2012
Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card.
IEEE J. Solid State Circuits, 2012
Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication.
IEEE J. Solid State Circuits, 2012
A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
IEICE Trans. Electron., 2012
6 W/25 mm<sup>2</sup> Wireless Power Transmission for Non-contact Wafer-Level Testing.
IEICE Trans. Electron., 2012
A 1 TB/s 1 pJ/b 6.4 mm<sup>2</sup>/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS.
Proceedings of the 2012 IEEE Radio and Wireless Symposium, 2012
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Session 23 overview: Advances in heterogeneous integration: Technology directions subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator.
Proceedings of the 38th European Solid-State Circuit conference, 2012
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012
A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012
2011
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2011
A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators.
IEEE Trans. Very Large Scale Integr. Syst., 2011
A 30 Gb/s/Link 2.2 Tb/s/mm <sup>2</sup> Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface.
IEEE J. Solid State Circuits, 2011
A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme.
IEEE J. Solid State Circuits, 2011
A 60-GHz Injection-Locked Frequency Divider Using Multi-Order <i>LC</i> Oscillator Topology for Wide Locking Range.
IEICE Trans. Electron., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the NOCS 2011, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 2.7Gb/s/mm<sup>2</sup> 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2010
47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing.
IEEE J. Solid State Circuits, 2010
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.
IEEE J. Solid State Circuits, 2010
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.
IEEE J. Solid State Circuits, 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Analysis of Inductive Coupling and Design of Rectifier Circuit for Inter-Chip Wireless Power Link.
IEICE Trans. Electron., 2010
A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme.
IEICE Trans. Electron., 2010
IEICE Trans. Electron., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEEE Commun. Mag., 2010
A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
An 8Tb/s 1pJ/b 0.8mm<sup>2</sup>/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Micro, 2009
IEEE J. Solid State Circuits, 2009
A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna.
IEEE J. Solid State Circuits, 2009
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A versatile recognition processor employing Haar-like feature and cascaded classifier.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the International Conference on Image Processing, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping.
IEEE J. Solid State Circuits, 2008
IEICE Trans. Electron., 2008
Proceedings of the Sixth Annual IEEE International Conference on Pervasive Computing and Communications (PerCom 2008), 2008
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the Seventh International Conference on Machine Learning and Applications, 2008
2007
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS.
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link.
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
IEICE Trans. Electron., 2007
IEICE Trans. Electron., 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI Package.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and ±2.5-cm range finding.
IEEE J. Solid State Circuits, 2006
A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package.
IEEE J. Solid State Circuits, 2006
IEICE Trans. Electron., 2006
Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect.
IEEE J. Solid State Circuits, 2005
2004
Transceiver circuits for pulse-based ultra-wideband.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A Real-Time Multi Face Detection Technique Using Positive-Negative Lines-of-Face Template.
Proceedings of the 17th International Conference on Pattern Recognition, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Optimization and control of <i>V</i><sub>DD</sub> and <i>V</i><sub>TH</sub> for low-power, high-speed CMOS design.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
2001
IEEE J. Solid State Circuits, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
IEEE J. Solid State Circuits, 2000
IEEE J. Solid State Circuits, 2000
1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
1998
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme.
IEEE J. Solid State Circuits, 1998
IEEE J. Solid State Circuits, 1998
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.
Proceedings of the 35th Conference on Design Automation, 1998
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1996
Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design.
J. VLSI Signal Process., 1996
Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability.
IEEE J. Solid State Circuits, 1996
A 0.9-V, 150-MHz, 10-mW, 4 mm<sup>2</sup>, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme.
IEEE J. Solid State Circuits, 1996
Substrate noise influence on circuit performance in variable threshold-voltage scheme.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1994
IEEE J. Solid State Circuits, May, 1994