Zhiqiang Cui

According to our database, Zhiqiang Cui authored at least 15 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Maintenance Spare Parts Prediction Based on Multilevel Migration Learning CNN-ISE-Attention-BiLSTM.

Zhiqiang Cui, Hongli Jia, Qi Gao, Haowen Song

IEEE Access, 2024

2023

The Use of Regional Data Assimilation to Improve Numerical Simulations of Diurnal Characteristics of Precipitation during an Active Madden-Julian Oscillation Event over the Maritime Continent.

Zhiqiang Cui, Zhaoxia Pu

Remote. Sens., May, 2023

2014

Multilevel error correction scheme for MLC flash memory.

Zhiqiang Cui, Zhongfeng Wang, Xinming Huang

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2011

Reduced-complexity column-layered decoding and implementation for LDPC codes.

Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang

IET Commun., 2011

2009

High-Throughput Layered LDPC Decoding Architecture.

Zhiqiang Cui, Zhongfeng Wang, Youjian Liu

IEEE Trans. Very Large Scale Integr. Syst., 2009

Towards an Optimal Trade-off of Viterbi Decoder Design.

Jinjin He, Zhongfeng Wang, Zhiqiang Cui, Li Li

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Improved low-complexity low-density parity-check decoding.

Zhiqiang Cui, Zhongfeng Wang

IET Commun., 2008

Extended layered decoding of LDPC codes.

Zhiqiang Cui, Zhongfeng Wang

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Efficient decoder design for high-throughput LDPC decoding.

Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang, Qingwei Jia

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes.

Zhongfeng Wang, Zhiqiang Cui

IEEE Trans. Very Large Scale Integr. Syst., 2007

Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes.

Zhongfeng Wang, Zhiqiang Cui

IEEE Trans. Very Large Scale Integr. Syst., 2007

Studies on Practical Low Complexity Decoding of Low-Density Parity-Check Codes.

Zhiqiang Cui, Zhongfeng Wang

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Efficient Message Passing Architecture for High Throughput LDPC Decoder.

Zhiqiang Cui, Zhongfeng Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Area-efficient parallel decoder architecture for high rate QC-LDPC codes.

Zhiqiang Cui, Zhongfeng Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA.

Zhiqiang Cui, Zhongfeng Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006