Li Li

Orcid: 0000-0002-1047-6067

Affiliations:
  • Nanjing University, Institute of VLSI Design, China


According to our database1, Li Li authored at least 83 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data.
IEEE Access, 2024

2023
A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow.
IEEE Des. Test, December, 2023

A DSP-Purposed REconfigurable Acceleration Machine (DREAM) for High Energy Efficiency MIMO Signal Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
A 67.5μJ/Prediction Accelerator for Spiking Neural Networks in Image Segmentation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Low-Latency Low-Complexity Method and Architecture for Computing Arbitrary Nth Root of Complex Numbers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Huicore: A Generalized Hardware Accelerator for Complicated Functions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Background Noise Adaptive Energy-Efficient Keywords Recognition Processor With Reusable DNN and Reconfigurable Architecture.
IEEE Access, 2022

Unsupervised Learning Based on Temporal Coding Using STDP in Spiking Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

AOME: Autonomous Optimal Mapping Exploration Using Reinforcement Learning for NoC-based Accelerators Running Neural Networks.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Work in Progress: ACAC: An Adaptive Congestion-aware Approximate Communication Mechanism for Network-on-Chip Systems.
Proceedings of the International Conference on Compilers, 2022

Deep Spiking Neural Network with Ternary Spikes.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

2021
Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Symmetric-Mapping LUT-Based Method and Architecture for Computing X<sup>Y</sup>-Like Functions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

IPD capacitor with pseudo-symmetry for isolated differential signal transfer applications.
Microelectron. J., 2021

<sup>2</sup>β-softmax: A Hardware-Friendly Activation Function with Low Complexity and High Performance.
Proceedings of the 18th International SoC Design Conference, 2021

Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT.
Proceedings of the 18th International SoC Design Conference, 2021

A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers.
Proceedings of the 18th International SoC Design Conference, 2021

Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANN.
Proceedings of the 18th International SoC Design Conference, 2021

LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC System.
Proceedings of the 18th International SoC Design Conference, 2021

Adaptive Successive Cancellation Priority Decoder for 5G Polar Codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation.
IEEE Trans. Circuits Syst., 2020

A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Efficient Successive Cancellation Stack Decoder for Polar Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2017
Kalman Predictor-Based Proactive Dynamic Thermal Management for 3-D NoC Systems With Noisy Thermal Sensors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Optimized sorting network for successive cancellation list decoding of polar codes.
IEICE Electron. Express, 2017

An access pattern based adaptive mapping function for GPGPU scratchpad memory.
IEICE Electron. Express, 2017

Application space exploration of a multi-fabric reconfigurable system.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Influences of an Aluminum Covering Layer on the Performance of Cross-Like Hall Devices.
Sensors, 2016

Design and implementation of high performance matrix inversion based on reconfigurable processor.
IEICE Electron. Express, 2016

An ultra-long FFT architecture implemented in a reconfigurable application specified processor.
IEICE Electron. Express, 2016

Floating-point operation based reconfigurable architecture for radar processing.
IEICE Electron. Express, 2016

A high throughput belief propagation decoder architecture for polar codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Performance Comparison of Cross-Like Hall Plates with Different Covering Layers.
Sensors, 2015

Exploring stacked main memory architecture for 3D GPGPUs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

An improved FFT architecture optimized for reconfigurable application specified processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A high performance parallel VLSI design of matrix inversion.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A survey of memory architecture for 3D chip multi-processors.
Microprocess. Microsystems, 2014

A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Monolithic H-bridge brushless DC vibration motor driver with a highly sensitive hall sensor in 0.18 μm complementary metal-oxide semiconductor technology.
IET Circuits Devices Syst., 2013

Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC.
Proceedings of the 10th IEEE International Conference on Control and Automation, 2013

Performance and power consumption analysis of memory efficient 3D network-on-chip architecture.
Proceedings of the 10th IEEE International Conference on Control and Automation, 2013

2012
Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications.
Sensors, 2012

2011
Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Flexible LDPC Decoder Design for Multigigabit-per-Second Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

An Efficient VLSI Architecture for Nonbinary LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Layered decoding for non-binary LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Application-level pipelining on Hierarchical NoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low power decoder design for QC-LDPC codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Multi-Gb/s LDPC Code Design and Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2009

An improved scaled DCT architecture.
IEEE Trans. Consumer Electron., 2009

LDPC decoder design for high rate wireless personal area networks.
IEEE Trans. Consumer Electron., 2009

Area-efficient reed-solomon decoder design for optical communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Decoder Design for RS-Based LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

An improved min-sum based column-layered decoding algorithm for LDPC codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

High-throughput GCM VLSI Architecture for IEEE 802.1ae Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Area-efficient Reed-Solomon Decoder Design for 10-100 Gb/s Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

LDPC Decoder Design for IEEE 802.15 Standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Towards an Optimal Trade-off of Viterbi Decoder Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A scalable distributed memory architecture for Network on Chip.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Low-complexity shift-LDPC decoder for high-speed communication systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Mapping algorithms of MIMO to a Multi-Pipeline Reconfigurable System.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
On the Implementation of Virtual Array Using Configuration Plane.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007

2006
An FPGA Implementation of Array LDPC Decoder.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


  Loading...