Zixiang Wan

According to our database, Zixiang Wan authored at least 4 papers between 2020 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation.

Xinyu Xu, Zixiang Wan, Woogeun Rhee, Zhihua Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops.

Zixiang Wan, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 0.0048mm² 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS.

Zixiang Wan, Xinyu Xu, Woogeun Rhee, Zhihua Wang

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020

A Nonlinearity-Calibration-Free Reconfigurable ADPLL for General Purpose Frequency Modulation.

Zixiang Wan, Woogeun Rhee, Zhihua Wang

Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020