Zizhang Luo

According to our database, Zizhang Luo authored at least 17 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Hive: A Multi-Agent Infrastructure for Algorithm- and Task-Level Scaling.

Zizhang Luo, Yuhao Luo, Youwei Xiao, Yansong Xu, Runlin Guo, Yun Liang

CoRR, April, 2026

Clover: A Neural-Symbolic Agentic Harness with Stochastic Tree-of-Thoughts for Verified RTL Repair.

Zizhang Luo, Yansong Xu, Runlin Guo, Fan Cui, Kexing Zhou, Mile Xia, Hongyuan Hou, Yuhao Luo, Yun Liang

CoRR, April, 2026

HWE-Bench: Benchmarking LLM Agents on Real-World Hardware Bug Repair Tasks.

Fan Cui, Hongyuan Hou, Zizhang Luo, Chenyun Yin, Yun Liang

CoRR, April, 2026

2025

R3A: Reliable RTL Repair Framework with Multi-Agent Fault Localization and Stochastic Tree-of-Thoughts Patch Generation.

Zizhang Luo, Fan Cui, Kexing Zhou, Runlin Guo, Mile Xia, Hongyuan Hou, Yun Liang

CoRR, November, 2025

Cement2: Temporal Hardware Transactions for High-Level and Efficient FPGA Programming.

Youwei Xiao, Zizhang Luo, Weijie Peng, Yuyang Zou, Yun Liang

CoRR, November, 2025

Clay: High-level ASIP Framework for Flexible Microarchitecture-Aware Instruction Customization.

Weijie Peng, Youwei Xiao, Yuyang Zou, Zizhang Luo, Yun (Eric) Liang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Cayman: Custom Accelerator Generation with Control Flow and Data Access Optimization.

Youwei Xiao, Fan Cui, Zizhang Luo, Weijie Peng, Yun Liang

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition.

Liqiang Lu, Zizhang Luo, Size Zheng, Jieming Yin, Jason Cong, Yun Liang, Jianwei Yin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis.

Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023

Automatic Generation of Spatial Accelerator for Tensor Algebra.

Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs.

Zizhang Luo, Liqiang Lu, Yicheng Jin, Liancheng Jia, Yun Liang

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition.

Zizhang Luo, Liqiang Lu, Size Zheng, Jieming Yin, Jason Cong, Jianwei Yin, Yun Liang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021

Sanger: A Co-Design Framework for Enabling Sparse Attention using Reconfigurable Architecture.

Liqiang Lu, Yicheng Jin, Hangrui Bi, Zizhang Luo, Peng Li, Tao Wang, Yun Liang

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs.

Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation.

Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra.

Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Teaching Platform for Network Communication and Protocols Using a Micro: bit Based Wheeled Robot.

Zizhang Luo, Yuxuan Zhou, Bohan Yu, Junfeng Hu

Proceedings of the 51st ACM Technical Symposium on Computer Science Education, 2020