Liancheng Jia

Orcid: 0000-0001-6682-035X

According to our database1, Liancheng Jia authored at least 11 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Automatic Generation of Spatial Accelerator for Tensor Algebra.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

TileFlow: A Framework for Modeling Fusion Dataflow via Tree-based Analysis.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022
Downscaling and Overflow-aware Model Compression for Efficient Vision Processors.
Proceedings of the 42nd IEEE International Conference on Distributed Computing Systems, 2022

EMS: efficient memory subsystem synthesis for spatial accelerators.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Enabling Efficient Fast Convolution Algorithms on GPUs via MegaKernels.
IEEE Trans. Computers, 2020

Generating Systolic Array Accelerators With Reusable Blocks.
IEEE Micro, 2020

2019
A coordinated tiling and batching framework for efficient GEMM on GPUs.
Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2019


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