Abbas Dandache

According to our database1, Abbas Dandache authored at least 61 papers between 1983 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Bibliography

2021
DWPT vs OFDM Under a Noisy Industrial Channel.
J. Ubiquitous Syst. Pervasive Networks, 2021

2020
Performance of IDWPT/DWPT compared with OFDM under an Industrial Channel.
Proceedings of the 11th International Conference on Ambient Systems, 2020

2019
Discrete Wavelet Packet Transform-Based Industrial Digital Wireless Communication Systems.
Inf., 2019

Emergency Patient's Arrivals Management Based on IoT and Discrete Simulation Using ARENA.
Proceedings of the Ubiquitous Networking - 5th International Symposium, 2019

Intelligent Patient Monitoring for Arrhythmia and Congestive Failure Patients Using Internet of Things and Convolutional Neural Network.
Proceedings of the 31st International Conference on Microelectronics, 2019

2017
Hybrid renewable energy installation for research and innovation: Case of Casablanca city in Morocco.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

IWSN under an industrial wireless channel in the context of Industry 4.0.
Proceedings of the 29th International Conference on Microelectronics, 2017

A ultra high speed and configurable Inverse Discrete Wavelet Packet Transform architecture.
Proceedings of the 29th International Conference on Microelectronics, 2017

A pure hardware k-SAT solver architecture for FPGA based on generic tree-search.
Proceedings of the 29th International Conference on Microelectronics, 2017

Modelling industrial manufacturing problem using ILP solver : Case of production analysis.
Proceedings of the 29th International Conference on Microelectronics, 2017

2016
A novel ultra high speed and configurable discrete wavelet packet transform architecture.
Proceedings of the 28th International Conference on Microelectronics, 2016

2015
LOS/NLOS Identification Based on Stable Distribution Feature Extraction and SVM Classifier for UWB On-Body Communications.
J. Ubiquitous Syst. Pervasive Networks, 2015

A new WSN transceiver based on DWPT for WBAN applications.
Proceedings of the 27th International Conference on Microelectronics, 2015

Bearing fault diagnosis based on Alpha-stable distribution feature extraction and wSVM classifier.
Proceedings of the 27th International Conference on Microelectronics, 2015

A low-cost design of transceiver based on DWPT for WSN.
Proceedings of the 27th International Conference on Microelectronics, 2015

A new FPGA-based DPLL algorithm to improve SAT solvers.
Proceedings of the 27th International Conference on Microelectronics, 2015

2014
Smart Reliable Network-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Configurable and high-throughput architectures for Quasi-cyclic low-density parity-check codes.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Snake Method Enhanced using Canny Approach Implementation for Cancer Cells Detection in Real Time .
Proceedings of the BIODEVICES 2014, 2014

2013
Robust chaotic key stream generator for real-time images encryption.
J. Real Time Image Process., 2013

Hybrid Fault Detection for Adaptive NoC.
IEEE Embed. Syst. Lett., 2013

Modeling and performance evaluations of Alamouti technique in a single frequency network for DVB-T2.
EURASIP J. Wirel. Commun. Netw., 2013

Design and FPGA implementation of a wireless hyperchaotic communication system for secure real-time image transmission.
EURASIP J. Image Video Process., 2013

A new auto-switched chaotic system and its FPGA implementation.
Commun. Nonlinear Sci. Numer. Simul., 2013

Embedded hyperchaotic Lorenz generator for secure communications.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012
A New Efficient and Reliable Dynamically Reconfigurable <i>Network-on-Chip</i>.
J. Electr. Comput. Eng., 2012

Experimental performance of mobile DVB-T2 in SFN and distributed MISO network.
Proceedings of the 19th International Conference on Telecommunications, 2012

Performance evaluation of SVC coding using MPLP-DVB-T2 for mobile and fixed reception.
Proceedings of the IEEE international Symposium on Broadband Multimedia Systems and Broadcasting, 2012

2011
A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture.
Int. J. Reconfigurable Comput., 2011

New hardware Cryptosystem based chaos for the secure real-time of embedded applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A dependable and dynamic network on chip suitable for FPGA-based reconfigurable systems.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Loopback output router for reliable Network on Chip.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Performance evaluation of distributed Tarokh SFBC and Alamouti MISO for SFN DVB-T2 broadcast networks.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Strategic placement of reliable routers for the optimization of dependable dynamic NoC.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Online Routing Fault Detection for Reconfigurable NoC.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Embedded Genesio-Tesi chaotic generator for ciphering communications.
Proceedings of the 7th International Symposium on Communication Systems Networks and Digital Signal Processing, 2010

An FPGA implementation of a Feed-Back Chaotic Synchronization for secure communications.
Proceedings of the 7th International Symposium on Communication Systems Networks and Digital Signal Processing, 2010

2009
Design of parallel fault-secure encoders for systematic cyclic block transmission codes.
Microelectron. J., 2009

A fault tolerant journalized stack processor architecture.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

An effective fast and small-area parallel-pipeline architecture for OTM-convolutional encoders.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Real time hardware implementation of a new Duffing's chaotic attractor.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A HW/SW mixed mechanism to improve the dependability of a stack processor.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Improving the design of parallel-pipeline cyclic decoders towards fault-secure versions.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

A cost-effective parallel architecture for the CodeRAKE receiver.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Characterizing Laser-Induced Pulses in ICs: Methodology and Results.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

CodeRAKE: a new small-area scalable architecture for the multi-user/multi-code RAKE receiver.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Digital Frequency Shift Keying Demodulator.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Modeling of Transients Caused by a Laser Attack on Smart Cards.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A multiprocessor architecture for fast packet processing.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
Design of a high speed parallel encoder for convolutional codes.
Microelectron. J., 2004

Designing a High Speed Decoder for Cyclic Codes.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

2003
Designing fault-secure parallel encoders for systematic linear error correcting codes.
IEEE Trans. Reliab., 2003

A methodology to design a multimedia processor core.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
A High Speed Encoder for Recursive Systematic Convolutive Codes.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001
Fast Configurable Polynomial Division for Error Control Coding Applications.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

1986
Conception de PLA CMOS. (CMOS PLA design).
PhD thesis, 1986

1983
Évaluations électriques et temporelles des PLA complexes COMPLETE : COM plex PLA Electrical and Temporal Evaluator.
PhD thesis, 1983


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