Stanislaw J. Piestrak

According to our database1, Stanislaw J. Piestrak authored at least 57 papers between 1987 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels.
J. Signal Process. Syst., 2018

Correction to: Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2<sup>k</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1, 2<sup>n+1</sup>-1, 2<sup>n-1</sup>-1} (<i>n</i> Even).
Circuits Syst. Signal Process., 2018

2017
Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2<sup>k</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1, 2<sup>n+1</sup>-1, 2<sup>n-1</sup>-1} (<i>n</i> Even).
Circuits Syst. Signal Process., 2017

Design of residue generators with CLA/compressor trees and multi-bit EAC.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016
Design of a low-power RNS-enhanced arithmetic unit.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015
A note on RNS architectures for the implementation of the diagonal function.
Inf. Process. Lett., 2015

Fault-tolerant implementation of direct FIR filters protected using residue codes.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Fault-aware configurable logic block for reliable reconfigurable FPGAs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Design of Reverse Converters for the New RNS Moduli Set {2<sup>n</sup>+1, 2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n-1</sup>+1} (<i>n</i> odd).
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design of Reverse Converters for General RNS Moduli Sets {2<sup>k</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1, 2<sup>n+1</sup>-1} and {2<sup>k</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1, 2<sup>n-1</sup>-1} (n even).
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design of the coarse-grained reconfigurable architecture DART with on-line error detection.
Microprocess. Microsystems, 2014

Private reliability environments for efficient fault-tolerance in CGRAs.
Des. Autom. Embed. Syst., 2014

Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor.
IEEE Trans. Computers, 2013

Implementation and evaluation of configuration scrubbing on CGRAs: A case study.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Design of an RNS reverse converter for a new five-moduli special set.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
Fast and energy-efficient constant-coefficient FIR filters using residue number system.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Design of multi-residue generators using shared logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Error recovery technique for coarse-grained reconfigurable architectures.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication".
IEEE Commun. Lett., 2010

Design of a fault-tolerant coarse-grained.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Design of cost-efficient multipliers modulo 2<sup>a</sup>-1.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Design of parallel fault-secure encoders for systematic cyclic block transmission codes.
Microelectron. J., 2009

Exploiting residue number system for power-efficient digital signal processing in embedded processors.
Proceedings of the 2009 International Conference on Compilers, 2009

2007
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006
Characterizing Laser-Induced Pulses in ICs: Methodology and Results.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2005
Modeling of Transients Caused by a Laser Attack on Smart Cards.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2003
Designing fault-secure parallel encoders for systematic linear error correcting codes.
IEEE Trans. Reliab., 2003

2002
Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'.
IEEE Trans. Computers, 2002

Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes.
IEEE Trans. Computers, 2002

Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
On the Design of Self-Testing Checkers for Modified Berger Codes.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

1999
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits.
Proceedings of the Dependable Computing, 1999

1998
Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters.
J. Electron. Test., 1998

VLSI implementation and complexity comparison of residue generators modulo 3.
Proceedings of the 9th European Signal Processing Conference, 1998

Membership Test Logic for Delay-Insensitive Codes.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997
Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
Design of minimal-level PLA self-testing checkers for m-out-of-n codes.
IEEE Trans. Very Large Scale Integr. Syst., 1996

Design of Self-Testing Checkers for Borden Codes.
IEEE Trans. Computers, 1996

Self-Checking Design in Eastern Europe.
IEEE Des. Test Comput., 1996

1995
Towards Totally Self-Checking Delay-Insensitive Systems.
Proceedings of the Digest of Papers: FTCS-25, 1995

Design of self-testing checkers for unidirectional error detecting codes.
PhD thesis, 1995

1994
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders.
IEEE Trans. Computers, 1994

Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks.
IEEE Trans. Computers, 1993

1991
Efficient Encoding? Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes.
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

Design of a Self-Testing Checker for Borden Code.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes.
IEEE Trans. Computers, 1990

The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

1987
Design of Fast Self-Testing Checkers for a Class of Berger Codes.
IEEE Trans. Computers, 1987


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