Fabrice Monteiro

According to our database1, Fabrice Monteiro authored at least 41 papers between 2000 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
DWPT vs OFDM Under a Noisy Industrial Channel.
J. Ubiquitous Syst. Pervasive Networks, 2021

2020
Performance of IDWPT/DWPT compared with OFDM under an Industrial Channel.
Proceedings of the 11th International Conference on Ambient Systems, 2020

2019
Discrete Wavelet Packet Transform-Based Industrial Digital Wireless Communication Systems.
Inf., 2019

2017
IWSN under an industrial wireless channel in the context of Industry 4.0.
Proceedings of the 29th International Conference on Microelectronics, 2017

A ultra high speed and configurable Inverse Discrete Wavelet Packet Transform architecture.
Proceedings of the 29th International Conference on Microelectronics, 2017

A pure hardware k-SAT solver architecture for FPGA based on generic tree-search.
Proceedings of the 29th International Conference on Microelectronics, 2017

Modelling industrial manufacturing problem using ILP solver : Case of production analysis.
Proceedings of the 29th International Conference on Microelectronics, 2017

2016
A novel ultra high speed and configurable discrete wavelet packet transform architecture.
Proceedings of the 28th International Conference on Microelectronics, 2016

2015
A new WSN transceiver based on DWPT for WBAN applications.
Proceedings of the 27th International Conference on Microelectronics, 2015

A low-cost design of transceiver based on DWPT for WSN.
Proceedings of the 27th International Conference on Microelectronics, 2015

A new FPGA-based DPLL algorithm to improve SAT solvers.
Proceedings of the 27th International Conference on Microelectronics, 2015

2014
Smart Reliable Network-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Configurable and high-throughput architectures for Quasi-cyclic low-density parity-check codes.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012
A New Efficient and Reliable Dynamically Reconfigurable <i>Network-on-Chip</i>.
J. Electr. Comput. Eng., 2012

2011
A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture.
Int. J. Reconfigurable Comput., 2011

Loopback output router for reliable Network on Chip.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Strategic placement of reliable routers for the optimization of dependable dynamic NoC.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Online Routing Fault Detection for Reconfigurable NoC.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Design of parallel fault-secure encoders for systematic cyclic block transmission codes.
Microelectron. J., 2009

A fault tolerant journalized stack processor architecture.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

An effective fast and small-area parallel-pipeline architecture for OTM-convolutional encoders.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

A HW/SW mixed mechanism to improve the dependability of a stack processor.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Improving the design of parallel-pipeline cyclic decoders towards fault-secure versions.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Stack processor architecture and development methods suitable for dependable applications.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

A cost-effective parallel architecture for the CodeRAKE receiver.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Characterizing Laser-Induced Pulses in ICs: Methodology and Results.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

CodeRAKE: a new small-area scalable architecture for the multi-user/multi-code RAKE receiver.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Teleoperation via Internet with Time-Varying Delay.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Digital Frequency Shift Keying Demodulator.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Modeling of Transients Caused by a Laser Attack on Smart Cards.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A multiprocessor architecture for fast packet processing.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
Design of a high speed parallel encoder for convolutional codes.
Microelectron. J., 2004

Designing a High Speed Decoder for Cyclic Codes.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

2003
Designing fault-secure parallel encoders for systematic linear error correcting codes.
IEEE Trans. Reliab., 2003

A methodology to design a multimedia processor core.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
A High Speed Encoder for Recursive Systematic Convolutive Codes.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001
Fast Configurable Polynomial Division for Error Control Coding Applications.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000


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