Abdelkrim Zitouni

According to our database1, Abdelkrim Zitouni authored at least 15 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Asynchronous dynamic arbiter for network on chip.
Int. J. Comput. Appl. Technol., 2021

2020
New Hardware Static and Reconfigurable Architectures for Video Watermarking System.
J. Circuits Syst. Comput., 2020

2018
A low-cost Exp_Golomb hardware architecture for H.264/AVC entropy coder.
Proceedings of the 30th International Conference on Microelectronics, 2018

Efficient Hybrid DWT-DCT Architecture for Wireless Capsule Endoscopy.
Proceedings of the 15th International Multi-Conference on Systems, Signals & Devices, 2018

A Design Platform for Reconfigurable Architecture and its Application to Watermarking System.
Proceedings of the 15th International Multi-Conference on Systems, Signals & Devices, 2018

2016
Design and evaluation of optimized router pipeline stages for network on chip.
Proceedings of the International Image Processing, Applications and Systems, 2016

2015
Low complexity and efficient architecture of 1D-DCT based Cordic-Loeffler for wireless endoscopy capsule.
Proceedings of the 12th IEEE International Multi-Conference on Systems, Signals & Devices, 2015

2013
A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme.
Integr., 2013

VCRBCM: A low latency virtual channel router architecture based on blocking controller manger.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

2012
System level modeling methodology of NoC design from UML-MARTE to VHDL.
Des. Autom. Embed. Syst., 2012

2011
FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2010
A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010

Design and implementation of low latency network interface for network on chip.
Proceedings of the 5th International Design and Test Workshop, 2010

2009
Nouvelles architectures génériques de NoC.
Tech. Sci. Informatiques, 2009

2008
Arbiter synthesis approach for SoC multi-processor systems.
Comput. Electr. Eng., 2008


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