Jean-Luc Dekeyser
Affiliations:- LIFL, Lille, France
According to our database1,
Jean-Luc Dekeyser
authored at least 138 papers
between 1990 and 2019.
Collaborative distances:
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Online presence:
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on www2.lifl.fr
On csauthors.net:
Bibliography
2019
Microprocess. Microsystems, 2019
ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures.
Int. J. Reconfigurable Comput., 2019
2018
IEEE Trans. Aerosp. Electron. Syst., 2018
A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip.
J. Parallel Distributed Comput., 2018
2017
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
2016
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
2015
Softw. Test. Verification Reliab., 2015
Adopting new learning strategies for computer architecture in higher education: case study: building the S3 microprocessor in 24 hours.
Proceedings of the Workshop on Computer Architecture Education, 2015
Using hardware parallelism for reducing power consumption in video streaming applications.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
2014
Adaptivity in high-performance embedded systems: a reactive control model for reliable and flexible design.
Knowl. Eng. Rev., 2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
2013
Microprocess. Microsystems, 2013
A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme.
Integr., 2013
Comput. Sci. Eng., 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
Microprocess. Microsystems, 2012
Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives.
J. Syst. Archit., 2012
Des. Autom. Embed. Syst., 2012
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012
Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012
An efficient power estimation methodology for complex RISC processor-based platforms.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone. Vers l'exploration à haut niveau de l'architecture.
Tech. Sci. Informatiques, 2011
ACM Trans. Embed. Comput. Syst., 2011
Int. J. Comput. Appl. Technol., 2011
EURASIP J. Embed. Syst., 2011
Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2011
CoRR, 2011
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 2011 International Symposium on System on Chip, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
2010
J. Syst. Archit., 2010
Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation.
Int. J. Embed. Syst., 2010
Parallel Sparse Matrix Solver on the GPU Applied to Simulation of Electrical Machines
CoRR, 2010
Proceedings of the Models in Software Engineering, 2010
A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the Reconfigurable Computing: Architectures, 2010
2009
Scalable Comput. Pract. Exp., 2009
Int. J. Reconfigurable Comput., 2009
Proceedings of the Software and Data Technologies - 4th International Conference, 2009
Traceability Mechanism for Error Localization in Model Transformation.
Proceedings of the ICSOFT 2009, 2009
A multi level functional verification of multistage interconnection network for MPSOC.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA.
Proceedings of the 7th IEEE/ACS International Conference on Computer Systems and Applications, 2009
2008
Innov. Syst. Softw. Eng., 2008
EURASIP J. Embed. Syst., 2008
Proceedings of the 16th Euromicro International Conference on Parallel, 2008
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008
Proceedings of the 9th International Symposium on Parallel Architectures, 2008
Unifying HW Analysis and SoC Design Flows by Bridging Two Key Standards: UML and IP-XACT.
Proceedings of the Distributed Embedded Systems: Design, 2008
Proceedings of the Forum on specification and Design Languages, 2008
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007
Multiple Abstraction Views of FPGA to Map Parallel Applications.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the Generative and Transformational Techniques in Software Engineering II, 2007
Proceedings of the FPL 2007, 2007
Model Transformations from a Data Parallel Formalism towards Synchronous Languages.
Proceedings of the Forum on specification and Design Languages, 2007
Proceedings of the Forum on specification and Design Languages, 2007
Proceedings of the 4th Conference on Computing Frontiers, 2007
2006
A universal performance factor for multi-criteria evaluation of multistage interconnection networks.
Future Gener. Comput. Syst., 2006
Proceedings of the 64th IEEE Vehicular Technology Conference, 2006
Proceedings of the International Symposium on System-on-Chip, 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the Forum on specification and Design Languages, 2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Proceedings of the Architecture of Computing Systems, 2006
2005
Proceedings of the Model Driven Engineering Languages and Systems, 2005
Model Driven Engineering for Regular MPSoC Co-design.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Proceedings of the Parallel Processing and Applied Mathematics, 2005
Proceedings of the 8th International Symposium on Parallel Architectures, 2005
Proceedings of the Hybrid Systems: Computation and Control, 8th International Workshop, 2005
Proceedings of the Forum on specification and Design Languages, 2005
Proceedings of the Forum on specification and Design Languages, 2005
2004
The Effect of the Degree of Multistage Interconnection Networks on their Performance: The Case of Delta and Over-Sized Delta Networks.
Proceedings of the 12th Euromicro Workshop on Parallel, 2004
An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Proceedings of the Virtual Enterprises and Collaborative Networks, IFIP 18th World Computer Congress, TC5 / WG5.5, 2004
Proceedings of the Architecture Description Languages, 2004
An automatic communication synthesis for high level SOC desing using transaction level modelling (poster).
Proceedings of the Forum on specification and Design Languages, 2004
MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications.
Proceedings of the Forum on specification and Design Languages, 2004
Proceedings of the Forum on specification and Design Languages, 2004
Proceedings of the Forum on specification and Design Languages, 2004
2003
Distributed Process Networks - Using Half FIFO Queues in CORBA.
Proceedings of the Parallel Computing: Software Technology, 2003
A Study of an Evaluation Methodology for Unbuffered Multistage Interconnection Networks.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Interoperability between Design and Simulation Tools using Model Transformation Techniques.
Proceedings of the Forum on specification and Design Languages, 2003
Proceedings of the Forum on specification and Design Languages, 2003
An Interconnection Networks Comparative Performance Evaluation Methodology: Delta and Over-Sized Delta Networks.
Proceedings of the ISCA 16th International Conference on Parallel and Distributed Computing Systems, 2003
2002
Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002
2001
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001
Proceedings of the Parallel Computing Technologies, 2001
2000
High Level Parallelization of a 3D Electromagnetic Simulation Code with Irregular Communication Patterns.
Proceedings of the Vector and Parallel Processing, 2000
Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000
1998
DPFS: A Data-Parallel File System Environment.
Proceedings of the High-Performance Computing and Networking, 1998
Proceedings of the High-Performance Computing and Networking, 1998
1997
Analysis and Simulation of an Out-Of-Order Execution Model in Vector Multiprocessor Systems.
Parallel Comput., 1997
Int. J. High Perform. Comput. Appl., 1997
Data Parallel File System.
Proceedings of the Eighth SIAM Conference on Parallel Processing for Scientific Computing, 1997
Step By Step Transformation of a Fortran 90 Program in HPF, using HPF-Builder.
Proceedings of the Eighth SIAM Conference on Parallel Processing for Scientific Computing, 1997
1996
Proceedings of the Vector and Parallel Processing, 1996
Mixed synchronous-asynchronous approach for real-time image processing: a MPEG-like coder.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996
Proceedings of the Euro-Par '96 Parallel Processing, 1996
Proceedings of the Data Parallel Programming Model: Foundations, 1996
1995
Analysis of Synchronous Dynamic Load Balancing Algorithms.
Proceedings of the Parallel Computing: State-of-the-Art and Perspectives, 1995
1994
Proceedings of the High-Performance Computing and Networking, 1994
Dynamic Load Balancing on SIMD Data-Parallel Computers.
Proceedings of the Massively Parallel Processing Applications and Develompent, 1994
1993
HelpDraw Graphical Environment: A Step Beyond Data Parallel Programming Languages.
Proceedings of the Human-Computer Interaction: Software and Hardware Interfaces, 1993
1992
Performance improvement for vector pipeline multiprocessor systems using a disordered execution model.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992
1990
Microprocessing and Microprogramming, 1990