Samy Meftali
Affiliations:- Université de Lille 1, France
According to our database1,
Samy Meftali
authored at least 45 papers
between 2001 and 2024.
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Bibliography
2024
A novel grey wolf optimization algorithm based on geometric transformations for gene selection and cancer classification.
J. Supercomput., March, 2024
2023
A new multi-objective binary Harris Hawks optimization for gene selection in microarray data.
J. Ambient Intell. Humaniz. Comput., 2023
2021
Hybridization of Moth flame optimization algorithm and quantum computing for gene selection in microarray data.
J. Ambient Intell. Humaniz. Comput., 2021
Gene selection and classification of microarray data method based on mutual information and moth flame algorithm.
Expert Syst. Appl., 2021
2020
Int. J. Embed. Syst., 2020
Proceedings of the 19th IEEE International Conference on Trust, 2020
2019
An Optimal Allocation of Tracking Tasks in a SW/HW Fog/Cloud Based Distributed Video Surveillance System.
J. Commun., 2019
2018
A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip.
J. Parallel Distributed Comput., 2018
A Survey of Keylogger and Screenlogger Attacks in the Banking Sector and Countermeasures to Them.
Proceedings of the Cyberspace Safety and Security - 10th International Symposium, 2018
2014
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
2013
Microprocess. Microsystems, 2013
A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme.
Integr., 2013
2012
Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives.
J. Syst. Archit., 2012
Des. Autom. Embed. Syst., 2012
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
EURASIP J. Embed. Syst., 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
2010
Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation.
Int. J. Embed. Syst., 2010
A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Vers la reconfiguration dynamique dans les systèmes embarqués: de la modélisation à l'implémentation. (Toward Dynamically Reconfigurable in Embedded Systems: From Models to Implementations).
, 2010
2009
Int. J. Reconfigurable Comput., 2009
2008
Proceedings of the 9th International Symposium on Parallel Architectures, 2008
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
2007
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007
Proceedings of the 4th Conference on Computing Frontiers, 2007
2006
Proceedings of the International Symposium on System-on-Chip, 2006
Proceedings of the Architecture of Computing Systems, 2006
2005
Proceedings of the 8th International Symposium on Parallel Architectures, 2005
Proceedings of the Forum on specification and Design Languages, 2005
Proceedings of the Forum on specification and Design Languages, 2005
2004
An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Proceedings of the Virtual Enterprises and Collaborative Networks, IFIP 18th World Computer Congress, TC5 / WG5.5, 2004
An automatic communication synthesis for high level SOC desing using transaction level modelling (poster).
Proceedings of the Forum on specification and Design Languages, 2004
MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications.
Proceedings of the Forum on specification and Design Languages, 2004
2002
Exploration d'architectures et allocation/affectation mémoire dans les systèmes multiprocesseurs mono puce = Architectures exploration and memory allocation/assignment in multiprocessor SoC. (Architectures exploration and memory allocation/assignment in multiprocessor SoC).
PhD thesis, 2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory.
Proceedings of the SOC Design Methodologies, 2001