Pierre Boulet

According to our database1, Pierre Boulet authored at least 63 papers between 1994 and 2022.

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Bibliography

2022
Progressive compression and weight reinforcement for spiking neural networks.
Concurr. Comput. Pract. Exp., 2022

How to Integrate Environmental Challenges in Computing Curricula?
Proceedings of the SIGCSE 2022: The 53rd ACM Technical Symposium on Computer Science Education, 2022

2021
VS2N : Interactive Dynamic Visualization and Analysis Tool for Spiking Neural Networks.
Proceedings of the 18th International Conference on Content-Based Multimedia Indexing, 2021

2020
Novel Metric for Load Balance and Congestion Reducing in Network on-Chip.
Scalable Comput. Pract. Exp., 2020

Measurement-based methodology for modelling the energy consumption of mobile devices.
Int. J. Reason. based Intell. Syst., 2020

2019
The Parallel Multi-Mode Digraph Task Model for Energy-Aware Real-Time Heterogeneous Multi-Core Systems.
IEEE Trans. Computers, 2019

Unsupervised visual feature learning with spike-timing-dependent plasticity: How far are we from traditional feature learning approaches?
Pattern Recognit., 2019

Multi-layered Spiking Neural Network with Target Timestamp Threshold Adaptation and STDP.
Proceedings of the International Joint Conference on Neural Networks, 2019

Spiking Neural Computing in Memristive Neuromorphic Platforms.
Proceedings of the Handbook of Memristor Networks., 2019

2018
Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures.
IEEE Trans. Multi Scale Comput. Syst., 2018

Mastering the Output Frequency in Spiking Neural Networks.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

2017
Memristor nanodevice for unconventional computing: review and applications.
CoRR, 2017

2016
Modeling Parallel Real-time Tasks with Di-Graphs.
Proceedings of the 24th International Conference on Real-Time Networks and Systems, 2016

Combining a volatile and nonvolatile memristor in artificial synapse to improve learning in Spiking Neural Networks.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

2015
Progressive and explicit refinement of scheduling for multidimensional data-flow applications using UML MARTE.
Des. Autom. Embed. Syst., 2015

2014
MID: A MetaCASE Tool for a Better Reuse of Visual Notations.
Proceedings of the System Analysis and Modeling: Models and Reusability, 2014

2013
Heuristics for Routing and Spiral Run-time Task Mapping in NoC-based Heterogeneous MPSOCs.
CoRR, 2013

A component-based approach for specifying reusable visual languages.
Proceedings of the 2013 IEEE Symposium on Visual Languages and Human Centric Computing, 2013

A component-based approach for specifying DSML's concrete syntax.
Proceedings of the Second Workshop on Graphical Modeling Language Development, 2013

2012
Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives.
J. Syst. Archit., 2012

System level modeling methodology of NoC design from UML-MARTE to VHDL.
Des. Autom. Embed. Syst., 2012

An Optimized Compilation of UML State Machines.
Proceedings of the 15th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2012

2011
Repetitive model refactoring strategy for the design space exploration of intensive signal processing applications.
J. Syst. Archit., 2011

Harnessing the Power of GPUs without Losing Abstractions in SAC and ArrayOL: A Comparative Study.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Array-OL with delays, a domain specific specification language for multidimensional intensive signal processing.
Multidimens. Syst. Signal Process., 2010

Does Code Generation Promote or Prevent Optimizations?
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2010

Architecture Exploration for Efficient Data Transfer and Storage in Data-Parallel Applications.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

Toward optimized code generation through model-based optimization.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems.
Scalable Comput. Pract. Exp., 2009

2008
Synchronous Modeling and Analysis of Data Intensive Applications.
EURASIP J. Embed. Syst., 2008

High Level Loop Transformations for Systematic Signal Processing Embedded Applications.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Modeling and Formal Validation of High-Performance Embedded Systems.
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008

Using an MDE Approach for Modeling of Interconnection Networks.
Proceedings of the 9th International Symposium on Parallel Architectures, 2008

2007
Multi-objective Mapping for NoC Architectures.
J. Digit. Inf. Manag., 2007

Repetitive Allocation Modelling with MARTE.
Proceedings of the Forum on specification and Design Languages, 2007

2006
UML2 Profile for Modeling Controlled Data Parallel Applications.
Proceedings of the Forum on specification and Design Languages, 2006

2005
Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies.
Proceedings of the Model Driven Engineering Languages and Systems, 2005

Model Driven Engineering for Regular MPSoC Co-design.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Model Driven Scheduling Framework for Multiprocessor SoC Design.
Proceedings of the Parallel Processing and Applied Mathematics, 2005

Projection of the Array-OL Specification Language onto the Kahn Process Network Computation Model.
Proceedings of the 8th International Symposium on Parallel Architectures, 2005

Mode-Automata Based Methodology for Scade.
Proceedings of the Hybrid Systems: Computation and Control, 8th International Workshop, 2005

Traceability and Interoperability in Models Transformations.
Proceedings of the Forum on specification and Design Languages, 2005

2004
Regular Hardware Architecture Modeling with UML2.
Proceedings of the Forum on specification and Design Languages, 2004

2003
Distributed Process Networks - Using Half FIFO Queues in CORBA.
Proceedings of the Parallel Computing: Software Technology, 2003

MDA for SoC Design, Intensive Signal Processing Experiment.
Proceedings of the Forum on specification and Design Languages, 2003

2002
Towards Distributed Process Networks with CORBA.
Scalable Comput. Pract. Exp., 2002

GASPARD - A Visual Parallel Programming Environment.
Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002

Contributions aux environnements de programmation pour le calcul intensif. (Contributions to intensive computing programming environment).
, 2002

2001
Recherche - SPPoC: manipulation automatique de polyèdres pour la compilation.
Tech. Sci. Informatiques, 2001

Visual Data-Parallel Programming for Signal Processing Applications.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

2000
High Level Parallelization of a 3D Electromagnetic Simulation Code with Irregular Communication Patterns.
Proceedings of the Vector and Parallel Processing, 2000

Parallelization of a 3D Magnetostatic Code Using High Performance Fortran.
Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000

1999
Algorithmic Issues on Heterogeneous Computing Platforms.
Parallel Process. Lett., 1999

Static tiling for heterogeneous computing platforms.
Parallel Comput., 1999

1998
Loop Parallelization Algorithms: From Parallelism Extraction to Code Generation.
Parallel Comput., 1998

Communication Pre-evaluation in HPF.
Proceedings of the Euro-Par '98 Parallel Processing, 1998

Scanning Polyhedra without Do-loops.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997
Code generation in bouclettes.
Proceedings of the Fifth Euromicro Workshop on Parallel and Distributed Processing (PDP '97), 1997

1996
Outils pour la parallélisation automatique. (Tools for automatic parallelization).
PhD thesis, 1996

Evaluation of Automatic Parallelization Strategies for HPF Compilers.
Proceedings of the High-Performance Computing and Networking, 1996

Bouclettes: A Fortran Loop Parallelizer.
Proceedings of the High-Performance Computing and Networking, 1996

1995
Evaluating Array Expressions On Massively Parallel Machines With Communication/ Computation Overlap.
Int. J. High Perform. Comput. Appl., 1995

1994
(Pen)-ultimate tiling?
Integr., 1994


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