Abdesattar Kalache

Orcid: 0000-0002-5560-3250

According to our database1, Abdesattar Kalache authored at least 5 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Headsail: One-Year Tape-Out of a 25-mm<sup>2</sup> Linux-Capable RISC-V MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., April, 2026

2025
Efficient and Predictable Context Switching for Mixed-Criticality and Real-Time Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2025

2024
Hardware Solutions for Eliminating Context Switching Latency in Processor-Based Hard Real-Time Systems.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

Atalanta: Open-Source RISC-V Microcontroller for Rust-Based Hard Real-Time Systems.
Proceedings of the Architecture of Computing Systems - 37th International Conference, 2024

2023
FPGA-based tunable Keccak core.
Proceedings of the International Conference on Smart Applications, 2023


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