Pekka Jääskeläinen

According to our database1, Pekka Jääskeläinen authored at least 74 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Exploiting Task Parallelism with OpenCL: A Case Study.
Signal Processing Systems, 2019

ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications.
Signal Processing Systems, 2019

LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor.
IEEE Trans. VLSI Syst., 2019

Blockwise Multi-Order Feature Regression for Real-Time Path-Tracing Reconstruction.
ACM Trans. Graph., 2019

Programmable and Scalable Architecture for Graphics Processing Units.
T. HiPEAC, 2019

Towards Efficient Code Generation for Exposed Datapath Architectures.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

SHRIMP: Efficient Instruction Delivery with Domain Wall Memory.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Reducing Computational Complexity of Real-Time Stereoscopic Ray Tracing with Spatiotemporal Sample Reprojection.
Proceedings of the 14th International Joint Conference on Computer Vision, 2019

AEx: Automated Customization of Exposed Datapath Soft-Cores.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Instruction Fetch Energy Reduction with Biased SRAMs.
Signal Processing Systems, 2018

Software Defined Radio Implementation of a Digital Self-interference Cancellation Method for Inband Full-Duplex Radio Using Mobile Processors.
Signal Processing Systems, 2018

PLOCTree: A Fast, High-Quality Hardware BVH Builder.
PACMCGIT, 2018

Variable Length Instruction Compression on Transport Triggered Architectures.
International Journal of Parallel Programming, 2018

Instantaneous foveated preview for progressive Monte Carlo rendering.
Computational Visual Media, 2018

Offloading C++17 Parallel STL on System Shared Virtual Memory Platforms.
Proceedings of the High Performance Computing, 2018

LoTTA: Energy-Efficient Processor for Always-On Applications.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

AivoTTA: an energy efficient programmable accelerator for CNN-based object recognition.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Energy-Delay Trade-Offs in Instruction Register File Design.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Transport Triggered Polar Decoders.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Transport-Triggered Soft Cores.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Sparse Sampling for Real-time Ray Tracing.
Proceedings of the 13th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP 2018), 2018

2017
Codesign Case Study on Transport-Triggered Architectures.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

MergeTree: A Fast Hardware HLBVH Constructor for Animated Ray Tracing.
ACM Trans. Graph., 2017

Fast Hardware Construction and Refitting of Quantized Bounding Volume Hierarchies.
Comput. Graph. Forum, 2017

Foveated instant preview for progressive rendering.
Proceedings of the SIGGRAPH Asia 2017 Technical Briefs, Bangkok, Thailand, November 27, 2017

Exposed datapath optimizations for loop scheduling.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

2016
Improving Code Density with Variable Length Encoding Aware Instruction Scheduling.
Signal Processing Systems, 2016

Integer Linear Programming-Based Scheduling for Transport Triggered Architectures.
TACO, 2016

Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Multi bounding volume hierarchies for ray tracing pipelines.
Proceedings of the SIGGRAPH ASIA 2016, Macao, December 5-8, 2016 - Technical Briefs, 2016

Aggressively bypassing list scheduler for transport triggered architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

OpenCL programmable exposed datapath high performance low-power image signal processor.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Foveated Path Tracing - A Literature Review and a Performance Gain Analysis.
Proceedings of the Advances in Visual Computing - 12th International Symposium, 2016

Customized high performance low power processor for binaural speaker localization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Half-precision Floating-point Ray Traversal.
Proceedings of the 11th Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP 2016), 2016

Software defined radio implementation of adaptive nonlinear digital self-interference cancellation for mobile inband full-duplex radio.
Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016

2015
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs.
Signal Processing Systems, 2015

Code Density and Energy Efficiency of Exposed Datapath Architectures.
Signal Processing Systems, 2015

Data Intensive Computing: From Modeling to Implementation.
Signal Processing Systems, 2015

pocl: A Performance-Portable OpenCL Implementation.
International Journal of Parallel Programming, 2015

MergeTree: a HLBVH constructor for mobile systems.
Proceedings of the SIGGRAPH Asia 2015 Technical Briefs, Kobe, Japan, November 2-6, 2015, 2015

Power optimizations for transport triggered SIMD processors.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Rapid customization of image processors using Halide.
Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015

Parallel processing intensive digital front-end for IEEE 802.11ac receiver.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Compiler optimizations for code density of variable length instructions.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Programmable in-loop deblock filter processor for video decoders.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Grover: Looking for Performance Improvement by Disabling Local Memory Usage in OpenCL Kernels.
Proceedings of the 43rd International Conference on Parallel Processing, 2014

Efficient software synthesis of dynamic dataflow programs.
Proceedings of the IEEE International Conference on Acoustics, 2014

A high throughput LDPC decoder using a mid-range GPU.
Proceedings of the IEEE International Conference on Acoustics, 2014

Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding.
Proceedings of the IEEE International Conference on Acoustics, 2014

Heuristics for greedy transport triggered architecture interconnect exploration.
Proceedings of the 2014 International Conference on Compilers, 2014

2013
Inexpensive correctly rounded floating-point division and square root with input scaling.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Low-power application-specific FFT processor for LTE applications.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Special session on "Exposed data path architectures: Recent advances and applications".
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Turbo decoding on tailored OpenCL processor.
Proceedings of the 2013 9th International Wireless Communications and Mobile Computing Conference, 2013

A 122Mb/s Turbo decoder using a mid-range GPU.
Proceedings of the 2013 9th International Wireless Communications and Mobile Computing Conference, 2013

Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

Simplified floating-point division and square root.
Proceedings of the IEEE International Conference on Acoustics, 2013

2011
Design Methodology for Offloading Software Executions to FPGA.
Signal Processing Systems, 2011

TCEMC: A co-design flow for application-specific multicores.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Customizable Datapath Integrated Lock Unit.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Operation set customization in retargetable compilers.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
OpenCL-based design methodology for application-specific processors.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Customized Exposed Datapath Soft-Core Design Flow with Compiler Support.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Reconfigurable video decoder with transform acceleration.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Programmable Accelerators for Reconfigurable Video Decoder.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Programmable and Scalable Architecture for Graphics Processing Units.
Proceedings of the Embedded Computer Systems: Architectures, 2009

2008
Resource conflict detection in simulation of function unit pipelines.
Journal of Systems Architecture - Embedded Systems Design, 2008

Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Reducing Context Switch Overhead with Compiler-Assisted Threading.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

2007
Resource Conflict Detection in Simulation of Function Unit Pipelines.
Proceedings of the Embedded Computer Systems: Architectures, 2007

2006
Software Pipelining Support for Transport Triggered Architecture Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2006


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