Joonas Multanen

According to our database, Joonas Multanen authored at least 24 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode.

Kari Hepola, Joonas Multanen, Pekka Jääskeläinen

IEEE Trans. Computers, February, 2024

Towards Efficient OpenCL Pipe Specification for Hardware Accelerators.

Topi Leppänen, Joonas Multanen, Leevi Leppänen, Pekka Jääskeläinen

Proceedings of the 12th International Workshop on OpenCL and SYCL, 2024

2023

AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors.

Alex Hirvonen, Topi Leppänen, Kari Hepola, Joonas Multanen, Joost Hoozemans, Pekka Jääskeläinen

J. Signal Process. Syst., September, 2023

Efficient OpenCL system integration of non-blocking FPGA accelerators.

Topi Leppänen, Atro Lotvonen, Panagiotis Mousouliotis, Joonas Multanen, Georgios Keramidas, Pekka Jääskeläinen

Microprocess. Microsystems, March, 2023

AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management.

Topi Leppänen, Joonas Multanen, Leevi Leppänen, Pekka Jääskeläinen

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

2022

Energy-Efficient Instruction Delivery in Embedded Systems With Domain Wall Memory.

Joonas Multanen, Kari Hepola, Asif Ali Khan, Jerónimo Castrillón, Pekka Jääskeläinen

IEEE Trans. Computers, 2022

OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors.

Kari Hepola, Joonas Multanen, Pekka Jääskeläinen

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism.

Kari Hepola, Joonas Multanen, Pekka Jääskeläinen

Proceedings of the Architecture of Computing Systems - 35th International Conference, 2022

2021

Energy-Efficient Instruction Streams for Embedded Processors.

Joonas Multanen

PhD thesis, 2021

Unified OpenCL Integration Methodology for FPGA Designs.

Topi Leppänen, Panagiotis Mousouliotis, Georgios Keramidas, Joonas Multanen, Pekka Jääskeläinen

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

2020

Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications.

Joonas Multanen, Heikki Kultala, Kati Tervo, Pekka Jääskeläinen

J. Signal Process. Syst., 2020

System Simulation of Memristor Based Computation in Memory Platforms.

Ali BanaGozar, Kanishkan Vadivel, Joonas Multanen, Pekka Jääskeläinen, Sander Stuijk, Henk Corporaal

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency.

Joonas Multanen, Kari Hepola, Pekka Jääskeläinen

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor.

Heikki Kultala, Timo Viitanen, Heikki Berg, Pekka Jääskeläinen, Joonas Multanen, Mikko Kokkonen, Kalle Raiskila, Tommi Zetterman, Jarmo Takala

IEEE Trans. Very Large Scale Integr. Syst., 2019

SHRIMP: Efficient Instruction Delivery with Domain Wall Memory.

Joonas Multanen, Pekka Jääskeläinen, Asif Ali Khan, Fazal Hameed, Jerónimo Castrillón

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018

Instruction Fetch Energy Reduction with Biased SRAMs.

Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala

J. Signal Process. Syst., 2018

Instantaneous foveated preview for progressive Monte Carlo rendering.

Matias Koskela, Kalle Immonen, Timo Viitanen, Pekka Jääskeläinen, Joonas Multanen, Jarmo H. Takala

Comput. Vis. Media, 2018

LoTTA: Energy-Efficient Processor for Always-On Applications.

Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen, Timo Viitanen, Aleksi Tervo, Jarmo Takala

Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Energy-Delay Trade-Offs in Instruction Register File Design.

Joonas Multanen, Heikki Kultala, Pekka Jääskeläinen

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

2017

Foveated instant preview for progressive rendering.

Matias Koskela, Kalle Immonen, Timo Viitanen, Pekka Jääskeläinen, Joonas Multanen, Jarmo Takala

Proceedings of the SIGGRAPH Asia 2017 Technical Briefs, Bangkok, Thailand, November 27, 2017

2016

Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies.

Joonas Multanen, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

OpenCL programmable exposed datapath high performance low-power image signal processor.

Joonas Multanen, Heikki Kultala, Matias Koskela, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala, Aram Danielyan, Cristóvão Cruz

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Customized high performance low power processor for binaural speaker localization.

Nicolai Behmann, Christopher Seifert, Guillermo Payá Vayá, Holger Blume, Pekka Jääskeläinen, Joonas Multanen, Heikki Kultala, Jarmo Takala, Joachim Thiemann, Steven van de Par

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

Power optimizations for transport triggered SIMD processors.

Joonas Multanen, Timo Viitanen, Henry Linjamaki, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Lauri Koskinen, Jesse Simonsson, Heikki Berg, Kalle Raiskila, Tommi Zetterman

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015