Abdullah M. Zyarah

According to our database1, Abdullah M. Zyarah authored at least 15 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2020
Neuromorphic System for Spatial and Temporal Information Processing.
IEEE Trans. Computers, 2020

End-to-End Memristive HTM System for Pattern Recognition and Sequence Prediction.
CoRR, 2020

FeFET-Based Neuromorphic Architecture with On-Device Feedback Alignment Training.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Metaplasticity in Multistate Memristor Synaptic Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Neuromorphic Architecture for the Hierarchical Temporal Memory.
IEEE Trans. Emerg. Top. Comput. Intell., 2019

Neuromemrisitive Architecture of HTM with On-Device Learning and Neurogenesis.
ACM J. Emerg. Technol. Comput. Syst., 2019

Neuromemristive Multi-Layer Random Projection Network with On-Device Learning.
Proceedings of the International Joint Conference on Neural Networks, 2019

2018
Semi-Trained Memristive Crossbar Computing Engine with <i>In Situ</i> Learning Accelerator.
ACM J. Emerg. Technol. Comput. Syst., 2018

Semi-Trained Memristive Crossbar Computing Engine with In-Situ Learning Accelerator.
CoRR, 2018

On-Device Learning in Memristor Spiking Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Invited paper: Resource sharing in feed forward neural networks for energy efficiency.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

On-device STDP and synaptic normalization for neuromemristive spiking neural network.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Ziksa: On-chip learning accelerator with memristor crossbars for multilevel neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Extreme learning machine as a generalizable classification engine.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

2015
Reconfigurable hardware architecture of the spatial pooler for hierarchical temporal memory.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015


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