Matthew J. Marinella

Orcid: 0000-0002-6537-1836

According to our database1, Matthew J. Marinella authored at least 43 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials.
Int. J. High Perform. Comput. Appl., July, 2023

Research Challenges for Energy-Efficient Computing in Automated Vehicles.
Computer, March, 2023

Enabling High-Speed, High-Resolution Space-based Focal Plane Arrays with Analog In-Memory Computing.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

TID Response of an Analog In-Memory Neural Network Accelerator.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Statistical Characterization of ReRAM Arrays for Analog In-Memory Computing.
Proceedings of the IEEE International Conference on Rebooting Computing, 2023

2022
An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Physical Compact Model for Three-Terminal SONOS Synaptic Circuit Element.
Adv. Intell. Syst., 2022

Eris: Fault Injection and Tracking Framework for Reliability Analysis of Open-Source Hardware.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Intrinsic Lateral Inhibition Facilitates Winner-Take-All in Domain Wall Racetrack Arrays for Neuromorphic Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Purely Spintronic Leaky Integrate-and-Fire Neurons.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Analog Neural Network Inference Accuracy in One-Selector One-Resistor Memory Arrays.
Proceedings of the IEEE International Conference on Rebooting Computing, 2022

2021
Shape-Dependent Multi-Weight Magnetic Artificial Synapses for Neuromorphic Computing.
CoRR, 2021

On the Accuracy of Analog Neural Network Inference Accelerators.
CoRR, 2021

High-Speed CMOS-Free Purely Spintronic Asynchronous Recurrent Neural Network.
CoRR, 2021

Controllable reset behavior in domain wall-magnetic tunnel junction artificial neurons for task-adaptable computation.
CoRR, 2021

An Analog Preconditioner for Solving Linear Systems.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
Memristor Model Optimization Based on Parameter Extraction From Device Characterization Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM.
IEEE Trans. Computers, 2020

Domain Wall Leaky Integrate-and-Fire Neurons with Shape-Based Configurable Activation Functions.
CoRR, 2020

Unsupervised Competitive Hardware Learning Rule for Spintronic Clustering Architecture.
CoRR, 2020

CMOS-Free Multilayer Perceptron Enabled by Four-Terminal MTJ Device.
CoRR, 2020

Evaluating complexity and resilience trade-offs in emerging memory inference machines.
Proceedings of the NICE '20: Neuro-inspired Computational Elements Workshop, 2020

Process Variation Model and Analysis for Domain Wall-Magnetic Tunnel Junction Logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

CMOS-Free Magnetic Domain Wall Leaky Integrate-and-Fire Neurons with Intrinsic Lateral Inhibition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Plasticity-Enhanced Domain-Wall MTJ Neural Networks for Energy-Efficient Online Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Device-aware inference operations in SONOS nonvolatile memory arrays.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Redox transistors for neuromorphic computing.
IBM J. Res. Dev., 2019

Shape-based Magnetic Domain Wall Drift for an Artificial Spintronic Leaky Integrate-and-Fire Neuron.
CoRR, 2019

Using Floating Gate Memory to Train Ideal Accuracy Neural Networks.
CoRR, 2019

Sparse Data Acquisition on Emerging Memory Architectures.
IEEE Access, 2019

Contrasting Advantages of Learning With Random Weights and Backpropagation in Non-Volatile Memory Neural Networks.
IEEE Access, 2019

Wafer-Scale TaOx Device Variability and Implications for Neuromorphic Computing Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2017
Ziksa: On-chip learning accelerator with memristor crossbars for multilevel neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016
Neuromemristive Systems: Boosting Efficiency through Brain-Inspired Computing.
Computer, 2016

Resistive memory device requirements for a neural algorithm accelerator.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

2015
Reconfigurable Memristive Device Technologies.
Proc. IEEE, 2015

Trapping characteristics and parametric shifts in lateral GaN HEMTs with SiO2/AlGaN gate stacks.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Memristors as Synapses in Artificial Neural Networks: Biomimicry Beyond Weight Change.
Proceedings of the Cybersecurity Systems for Human Cognition Augmentation, 2014

Degenerate Resistive Switching and Ultrahigh Density Storage in Resistive Memory.
CoRR, 2014

Emerging resistive switching memory technologies: Overview and current status.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014


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